Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) Supply TSSOP 16

8 9

CS SCLK

DOUT

AGND DIN

IN0 V

IN1 DGND

IN2 IN7

IN3 IN6

IN4 IN5

ADC128S102

www.ti.com

SNAS298F –AUGUST 2005–REVISED MAY 2013

ADC128S102 8-Channel, 500 ksps to 1 Msps, 12-Bit A/D Converter

Check for Samples: ADC128S102

FEATURES

DESCRIPTION

The ADC128S102 is a low-power, eight-channel

234

• Eight Input Channels

CMOS 12-bit analog-to-digital converter specified for

• Variable Power Management

conversion throughput rates of 500 ksps to 1 MSPS.

• Independent Analog and Digital Supplies

The converter is based on a successive-

approximation register architecture with an internal

• SPI™/ QSPI™/ MICROWIRE™/DSP Compatible

track-and-hold circuit. It can be configured to accept

• Packaged in 16-Lead TSSOP

up to eight input signals at inputs IN0 through IN7.

The output serial data is straight binary and is

APPLICATIONS

compatible with several standards, such as SPI™,

• Automotive Navigation

QSPI™, MICROWIRE™, and many common DSP

• Portable Systems

serial interfaces.

• Medical Instruments

The ADC128S102 may be operated with independent

• Mobile Communications

analog and digital supplies. The analog supply (V

)

can range from +2.7V to +5.25V, and the digital

• Instrumentation and Control Systems

supply (V

) can range from +2.7V to V

. Normal

power consumption using a +3V or +5V supply is 2.3

KEY SPECIFICATIONS

mW and 10.7 mW, respectively. The power-down

• Conversion Rate 500 ksps to 1 MSPS

feature reduces the power consumption to 0.06 µW

using a +3V supply and 0.25 µW using a +5V supply.

• DNL (V

= V

= 5.0 V) +1.5 / −0.9

The ADC128S102 is packaged in a 16-lead TSSOP

• LSB (max) INL (V

= V

= 5.0 V) ±1.2 LSB (max)

package. Operation over the extended industrial

• Power Consumption

temperature range of −40°C to +105°C is ensured.

– 3V Supply 2.3 mW (typ)

– 5V Supply 10.7 mW (typ)

Connection Diagram

Figure 1. TSSOP Package

See Package Number PW0016A

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2MICROWIRE is a trademark of Texas Instruments.

3SPI, QSPI are trademarks of Motorola, Inc..

4All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (25 pages)

PAGE 1
ADC128S102 www.ti.com SNAS298F – AUGUST 2005 – REVISED MAY 2013 ADC128S102 8-Channel, 500 ksps to 1 Msps, 12-Bit A/D Converter Check for Samples: ADC128S102 FEATURES DESCRIPTION • • • • • The ADC128S102 is a low-power, eight-channel CMOS 12-bit analog-to-digital converter specified for conversion throughput rates of 500 ksps to 1 MSPS. The converter is based on a successiveapproximation register architecture with an internal track-and-hold circuit.
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ADC128S102 SNAS298F – AUGUST 2005 – REVISED MAY 2013 www.ti.com Block Diagram IN0 . . . T/H MUX VA 12-BIT SUCCESSIVE APPROXIMATION ADC AGND AGND IN7 VD SCLK ADC128S102 CS CONTROL LOGIC DIN DOUT DGND Pin Descriptions Pin No. Name Description ANALOG I/O 4 - 11 IN0 to IN7 Analog inputs. These signals can range from 0V to VREF. DIGITAL I/O 16 SCLK Digital clock input. The ensured performance range of frequencies for this input is 8 MHz to 16 MHz.
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ADC128S102 www.ti.com SNAS298F – AUGUST 2005 – REVISED MAY 2013 Absolute Maximum Ratings (1) (2) Analog Supply Voltage VA −0.3V to 6.5V Digital Supply Voltage VD −0.3V to VA + 0.3V, max 6.5V Voltage on Any Pin to GND −0.3V to VA +0.3V (3) ±10 mA Input Current at Any Pin Package Input Current (3) ±20 mA Power Dissipation at TA = 25°C ESD Susceptibility (5) See Human Body Model (4) 2500V Machine Model 250V For soldering specifications: see product folder at www.ti.com and http://www.ti.
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ADC128S102 SNAS298F – AUGUST 2005 – REVISED MAY 2013 www.ti.com ADC128S102 Converter Electrical Characteristics (1) The following specifications apply for AGND = DGND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 ksps to 1 MSPS, CL = 50pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
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ADC128S102 www.ti.com SNAS298F – AUGUST 2005 – REVISED MAY 2013 ADC128S102 Converter Electrical Characteristics (1) (continued) The following specifications apply for AGND = DGND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 ksps to 1 MSPS, CL = 50pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
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ADC128S102 SNAS298F – AUGUST 2005 – REVISED MAY 2013 www.ti.com ADC128S102 Converter Electrical Characteristics (1) (continued) The following specifications apply for AGND = DGND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 ksps to 1 MSPS, CL = 50pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Parameter Test Conditions Typical Limits (2) Units AC ELECTRICAL CHARACTERISTICS fSCLKMIN Minimum Clock Frequency VA = VD = +2.7V to +5.
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ADC128S102 www.ti.com SNAS298F – AUGUST 2005 – REVISED MAY 2013 TIMING DIAGRAMS Power Down Power Up Track Power Up Hold Track Hold CS 1 2 3 4 5 6 8 7 9 10 11 12 13 14 15 1 16 2 3 4 5 6 7 8 SCLK Control register DIN DOUT ADD2 ADD1 ADD0 ADD2 ADD1 DB11 DB10 DB9 FOUR ZEROS DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 FOUR ZEROS DB0 ADD0 DB11 DB10 DB9 Figure 2.
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ADC128S102 SNAS298F – AUGUST 2005 – REVISED MAY 2013 www.ti.com DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the SCLK. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.
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ADC128S102 www.ti.com SNAS298F – AUGUST 2005 – REVISED MAY 2013 Typical Performance Characteristics TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated. DNL DNL Figure 5. Figure 6. INL INL Figure 7. Figure 8. DNL vs. Supply INL vs. Supply Figure 9. Figure 10.
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ADC128S102 SNAS298F – AUGUST 2005 – REVISED MAY 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated. 10 SNR vs. Supply THD vs. Supply Figure 11. Figure 12. ENOB vs. Supply DNL vs. VD with VA = 5.0 V Figure 13. Figure 14. INL vs. VD with VA = 5.0 V DNL vs. SCLK Duty Cycle Figure 15. Figure 16.
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ADC128S102 www.ti.com SNAS298F – AUGUST 2005 – REVISED MAY 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated. INL vs. SCLK Duty Cycle SNR vs. SCLK Duty Cycle Figure 17. Figure 18. THD vs. SCLK Duty Cycle ENOB vs. SCLK Duty Cycle Figure 19. Figure 20. DNL vs. SCLK INL vs. SCLK Figure 21. Figure 22.
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ADC128S102 SNAS298F – AUGUST 2005 – REVISED MAY 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated. 12 SNR vs. SCLK THD vs. SCLK Figure 23. Figure 24. ENOB vs. SCLK DNL vs. Temperature Figure 25. Figure 26. INL vs. Temperature SNR vs. Temperature Figure 27. Figure 28.
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ADC128S102 www.ti.com SNAS298F – AUGUST 2005 – REVISED MAY 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated. THD vs. Temperature ENOB vs. Temperature Figure 29. Figure 30. SNR vs. Input Frequency THD vs. Input Frequency Figure 31. Figure 32. ENOB vs. Input Frequency Power Consumption vs. SCLK Figure 33. Figure 34.
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ADC128S102 SNAS298F – AUGUST 2005 – REVISED MAY 2013 www.ti.com FUNCTIONAL DESCRIPTION The ADC128S102 is a successive-approximation analog-to-digital converter designed around a chargeredistribution digital-to-analog converter. ADC128S102 OPERATION Simplified schematics of the ADC128S102 in both track and hold operation are shown in Figure 35 and Figure 36 respectively.
PAGE 15
ADC128S102 www.ti.com SNAS298F – AUGUST 2005 – REVISED MAY 2013 During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13 SCLK cycles the conversion is accomplished and the data is clocked out. SCLK falling edges 1 through 4 clock out leading zeros while falling edges 5 through 16 clock out the conversion result, MSB first.
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ADC128S102 SNAS298F – AUGUST 2005 – REVISED MAY 2013 www.ti.com 111...111 111...000 | | ADC CODE 111...110 1LSB = VA/4096 011...111 000...010 | 000...001 000...000 0V 0.5LSB ANALOG INPUT +VA - 1.5LSB Figure 37. Ideal Transfer Characteristic ANALOG INPUTS An equivalent circuit for one of the ADC128S102's input channels is shown in Figure 38. Diodes D1 and D2 provide ESD protection for the analog inputs. The operating range for the analog inputs is 0 V to VA.
PAGE 17
ADC128S102 www.ti.com SNAS298F – AUGUST 2005 – REVISED MAY 2013 Applications Information TYPICAL APPLICATION CIRCUIT A typical application is shown in Figure 39. The split analog and digital supply pins are both powered in this example by the TI LP2950 low-dropout voltage regulator. The analog supply is bypassed with a capacitor network located close to the ADC128S102. The digital supply is separated from the analog supply by an isolation resistor and bypassed with additional capacitors.
PAGE 18
ADC128S102 SNAS298F – AUGUST 2005 – REVISED MAY 2013 www.ti.com Power Supply Noise Considerations The charging of any output load capacitance requires current from the digital supply, VD. The current pulses required from the supply to charge the output capacitance will cause voltage variations on the digital supply. If these variations are large enough, they could degrade SNR and SINAD performance of the ADC.
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ADC128S102 www.ti.com SNAS298F – AUGUST 2005 – REVISED MAY 2013 REVISION HISTORY Changes from Revision D (March 2013) to Revision E • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADC128S102CIMTX/NOP B Package Package Pins Type Drawing TSSOP PW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 8.3 1.6 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device ADC128S102CIMTX/NOP B Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TSSOP PW 16 2500 367.0 367.0 35.
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