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ADC12DC105

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SNAS469A –SEPTEMBER 2008–REVISED OCTOBER 2008

ADC12DC105 Dual 12-Bit, 105 MSPS A/D Converter with CMOS Outputs

Check for Samples: ADC12DC105

FEATURES

DESCRIPTION

The ADC12DC105 is a high-performance CMOS

• Internal Sample-and-Hold Circuit and Precision

analog-to-digital converter capable of converting two

Reference

analog input signals into 12-bit digital words at rates

• Low Power Consumption

up to 105 Mega Samples Per Second (MSPS). These

• Clock Duty Cycle Stabilizer

converters use a differential, pipelined architecture

with digital error correction and an on-chip sample-

• Single +3.0V or +3.3V Supply Operation

and-hold circuit to minimize power consumption and

• Power-Down Mode

the external component count, while providing

• Offset Binary or 2's Complement Output Data

excellent dynamic performance. A unique sample-

Format

and-hold stage yields a full-power bandwidth of 1

GHz. The ADC12DC080/105 may be operated from a

• 60-Pin WQFN Package, (9x9x0.8mm, 0.5mm

single +3.0V or +3.3V power supply. A power-down

Pin-Pitch)

feature reduces the power consumption to very low

levels while still allowing fast wake-up time to full

APPLICATIONS

operation. The differential inputs provide a 2V full

scale differential input swing. A stable 1.2V internal

• High IF Sampling Receivers

voltage reference is provided, or the ADC12DC105

• Wireless Base Station Receivers

can be operated with an external 1.2V reference.

• Test and Measurement Equipment

Output data format (offset binary versus 2's

• Communications Instrumentation

complement) and duty cycle stabilizer are pin-

selectable. The duty cycle stabilizer maintains

• Portable Instrumentation

performance over a wide range of clock duty cycles.

KEY SPECIFICATIONS

The ADC12DC105 is available in a 60-lead WQFN

package and operates over the industrial temperature

• Resolution: 12 Bits

range of −40°C to +85°C.

• Conversion Rate: 105 MSPS

• SNR (f

= 170 MHz): 69 dBFS (Typ)

• SFDR (f

= 170 MHz): 83 dBFS (Typ)

• Full Power Bandwidth: 1 GHz (Typ)

• Power Consumption

– 690 mW (Typ), V

= 3.0V

– 800 mW (Typ), V

= 3.3V

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (24 pages)

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ADC12DC105 www.ti.com SNAS469A – SEPTEMBER 2008 – REVISED OCTOBER 2008 ADC12DC105 Dual 12-Bit, 105 MSPS A/D Converter with CMOS Outputs Check for Samples: ADC12DC105 FEATURES DESCRIPTION • The ADC12DC105 is a high-performance CMOS analog-to-digital converter capable of converting two analog input signals into 12-bit digital words at rates up to 105 Mega Samples Per Second (MSPS).
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ADC12DC105 SNAS469A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com Block Diagram 2 12 12-Bit Pipelined ADC Core VINA Output Buffers 12 CHANNEL A DA0-DA11 3 Ref.Decoupling VREF Reference A Timing Generation CLK Ref.
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ADC12DC105 www.ti.com SNAS469A – SEPTEMBER 2008 – REVISED OCTOBER 2008 PIN DESCRIPTIONS Pin No. Symbol Equivalent Circuit Description ANALOG I/O 3 13 2 14 VINA+ VINB+ VA Differential analog input pins. The differential full-scale input signal level is 2VP-P with each input pin signal centered on a common mode voltage, VCM. VINAVINBAGND (1) 5 11 VRPA VRPB 7 9 VCMOA VCMOB VA VA These pins should each be bypassed to AGND with a low ESL (equivalent series inductance) 0.
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ADC12DC105 SNAS469A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com PIN DESCRIPTIONS (continued) Pin No. Symbol Equivalent Circuit VDR Description Digital data output pins that make up the 12-bit conversion result for Channel A. DA0 (pin 42) is the LSB, while DA11 (pin 55) is the MSB of the output word. Output levels are CMOS compatible. VA 42-49, 52-55 DA0-DA7, DA8-DA11 23-24, 27-36 DB0-DB1, DB3-DB11 Digital data output pins that make up the 12-bit conversion result for Channel B.
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ADC12DC105 www.ti.com SNAS469A – SEPTEMBER 2008 – REVISED OCTOBER 2008 Operating Ratings (1) (2) −40°C ≤ TA ≤ +85°C Operating Temperature Supply Voltage (VA) +2.7V to +3.6V Output Driver Supply (VDR) +2.4V to VA (DCS Enabled) Clock Duty Cycle 30/70 % (DCS Disabled) 45/55 % VCM 1.4V to 1.6V ≤100mV |AGND-DRGND| (1) (2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
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ADC12DC105 SNAS469A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com Converter Electrical Characteristics (continued) Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX.
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ADC12DC105 www.ti.com SNAS469A – SEPTEMBER 2008 – REVISED OCTOBER 2008 Dynamic Converter Electrical Characteristics (continued) Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin, . Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX.
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ADC12DC105 SNAS469A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com Logic and Power Supply Electrical Characteristics (continued) Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX.
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ADC12DC105 www.ti.com SNAS469A – SEPTEMBER 2008 – REVISED OCTOBER 2008 Specification Definitions APERTURE DELAY is the time after the falling edge of the clock to when the input signal is acquired or held for conversion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the total time of one period.
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ADC12DC105 SNAS469A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or DC.
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ADC12DC105 www.ti.com SNAS469A – SEPTEMBER 2008 – REVISED OCTOBER 2008 Transfer Characteristic Figure 3.
PAGE 12
ADC12DC105 SNAS469A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com Typical Performance Characteristics DNL, INL Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, TA = 25°C. 12 DNL INL Figure 4. Figure 5.
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ADC12DC105 www.ti.com SNAS469A – SEPTEMBER 2008 – REVISED OCTOBER 2008 Typical Performance Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, fIN = 170 MHz, TA = 25°C. SNR, SINAD, SFDR vs. VA Distortion vs. VA Figure 6. Figure 7. SNR, SINAD, SFDR vs. Clock Duty Cycle, fIN=40 MHz Distortion vs. Clock Duty Cycle, fIN=40 MHz Figure 8. Figure 9.
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ADC12DC105 SNAS469A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, fIN = 170 MHz, TA = 25°C. 14 SNR and SFDR vs. fIN POWER vs. fCLK Figure 12. Figure 13. Spectral Response @ 10 MHz Input Spectral Response @ 70 MHz Input Figure 14. Figure 15.
PAGE 15
ADC12DC105 www.ti.com SNAS469A – SEPTEMBER 2008 – REVISED OCTOBER 2008 Functional Description Operating on a single +3.0V or +3.3V supply, the ADC12DC105 digitizes two differential analog input signals to 12 bits, using a differential pipelined architecture with error correction circuitry and an on-chip sample-and-hold circuit to ensure maximum performance. The user has the choice of using an internal 1.2V stable reference, or using an external 1.2V reference.
PAGE 16
ADC12DC105 SNAS469A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com For single frequency sine waves the full scale error in LSB can be described as approximately: EFS = 4096 ( 1 - sin (90° + dev)) where • dev is the angular difference in degrees between the two signals having a 180° relative phase relationship to each other (see Figure 19) (11) For single frequency inputs, angular errors result in a reduction of the effective full scale input.
PAGE 17
ADC12DC105 www.ti.com SNAS469A – SEPTEMBER 2008 – REVISED OCTOBER 2008 Driving the Analog Inputs The VIN+ and the VIN− inputs of the ADC12DC105 have an internal sample-and-hold circuit which consists of an analog switch followed by a switched-capacitor amplifier. Figure 20 and Figure 21 show examples of single-ended to differential conversion circuits. The circuit in Figure 20 works well for input frequencies up to approximately 70MHz, while the circuit in Figure 21 works well above 70MHz. VIN 0.
PAGE 18
ADC12DC105 SNAS469A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com Smaller capacitor values than those specified will allow faster recovery from the power down mode, but may result in degraded noise performance. Loading any of these pins, other than VCMO may result in performance degradation. The nominal voltages for the reference bypass pins are as follows: VCMO = 1.5 V VRP = 2.0 V VRN = 1.
PAGE 19
ADC12DC105 www.ti.com SNAS469A – SEPTEMBER 2008 – REVISED OCTOBER 2008 DIGITAL OUTPUTS Digital outputs consist of the CMOS signals DA0-DA11, DB0-DB11, and DRDY. The ADC12DC105 has 12 CMOS compatible data output pins corresponding to the converted input value for each channel, and a data ready (DRDY) signal that should be used to capture the output data. Valid data is present at these outputs while the PD pin is low. Data should be captured and latched with the rising edge of the DRDY signal.
PAGE 20
ADC12DC105 SNAS469A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com LAYOUT AND GROUNDING Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining separate analog and digital areas of the board, with the ADC12DC105 between these areas, is required to achieve specified performance. Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor performance.
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PACKAGE OPTION ADDENDUM www.ti.
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MECHANICAL DATA NKA0060A SQA60A (Rev A) www.ti.
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