Datasheet
V
A
AGND
To Internal Circuitry
I/O
ADC12DC105
SNAS469A –SEPTEMBER 2008–REVISED OCTOBER 2008
www.ti.com
Logic and Power Supply Electrical Characteristics (continued)
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V
A
= +3.3V, V
DR
= +2.5V, Internal V
REF
= +1.2V, f
CLK
= 105 MHz, V
CM
= V
CMO
, C
L
= 5 pF/pin. Typical values are for T
A
= 25°C. Boldface limits apply for T
MIN
≤ T
A
≤
T
MAX
. All other limits apply for T
A
= 25°C
(1)(2)(3)
Units
Parameter Test Conditions Typical
(4)
Limits
(Limits)
DIGITAL OUTPUT CHARACTERISTICS (DA0-DA11,DB0-DB11,DRDY)
V
OUT(1)
Logical “1” Output Voltage I
OUT
= −0.5 mA , V
DR
= 2.4V 2.0 V (min)
V
OUT(0)
Logical “0” Output Voltage I
OUT
= 1.6 mA, V
DR
= 2.4V 0.4 V (max)
+I
SC
Output Short Circuit Source Current V
OUT
= 0V −10 mA
−I
SC
Output Short Circuit Sink Current V
OUT
= V
DR
10 mA
C
OUT
Digital Output Capacitance 5 pF
POWER SUPPLY CHARACTERISTICS
I
A
Analog Supply Current Full Operation 242 273 mA (max)
I
DR
Digital Output Supply Current Full Operation
(5)
32 mA
Power Consumption Excludes I
DR
(5)
800 900 mW (max)
Power Down Power Consumption PD_A=PD_B=V
A
33 mW
(5) I
DR
is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins,
the supply voltage, V
DR
, and the rate at which the outputs are switching (which is signal dependent). I
DR
=V
DR
(C
0
x f
0
+ C
1
x f
1
+....C
11
x
f
11
) where V
DR
is the output driver power supply voltage, C
n
is total capacitance on the output pin, and f
n
is the average frequency at
which that pin is toggling.
Timing and AC Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V
A
= +3.3V, V
DR
= +2.5V, Internal V
REF
= +1.2V, f
CLK
= 105 MHz, V
CM
= V
CMO
, C
L
= 5 pF/pin. Typical values are for T
A
= 25°C. Timing measurements are taken at
50% of the signal amplitude. Boldface limits apply for T
MIN
≤ T
A
≤ T
MAX
. All other limits apply for T
A
= 25°C
(1)(2)(3)
Units
Parameter Test Conditions Typical
(4)
Limits
(Limits)
Maximum Clock Frequency 105 MHz (max)
Minimum Clock Frequency 20 MHz (min)
t
CH
Clock High Time 4 ns
t
CL
Clock Low Time 4 ns
t
CONV
Conversion Latency 7 Clock Cycles
4.6 ns (min)
t
OD
Output Delay of CLK to DATA Relative to rising edge of CLK 6.7
8.8 ns (max)
t
SU
Data Output Setup Time Relative to DRDY 4 3 ns (min)
t
H
Data Output Hold Time Relative to DRDY 5.5 3.8 ns (min)
t
AD
Aperture Delay 0.6 ns
t
AJ
Aperture Jitter 0.1 ps rms
(1) The inputs are protected as shown below. Input voltage magnitudes above V
A
or below GND will not damage this device, provided
current is limited. However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described in the
Operating Ratings section.
(2) With a full scale differential input of 2V
P-P
, the 12-bit LSB is 488 µV.
(3) When the input voltage at any pin exceeds the power supplies (that is, V
IN
< AGND, or V
IN
> V
A
), the current at that pin should be
limited to ±5 mA. The ±50 mA maximum package input current rating limits the number of pins that can safely exceed the power
supplies with an input current of ±5 mA to 10.
(4) Typical figures are at T
A
= 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not guaranteed.
8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Links: ADC12DC105