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ADC141S626

www.ti.com

SNAS434B –NOVEMBER 2007–REVISED MARCH 2013

ADC141S626 14-Bit, 50 kSPS to 250 kSPS, Differential Input, Micro Power A/D Converter

Check for Samples: ADC141S626

FEATURES

DESCRIPTION

• True Differential Inputs

The ADC141S626 is a 14-bit, 50 kSPS to 250 kSPS

• Guaranteed Performance from 50 kSPS to 250

sampling Analog-to-Digital (A/D) converter. The

kSPS

converter is based on a successive-approximation

• External Reference

nature of the analog inputs is maintained from the

• Zero-Power Track Mode

internal sample-and-hold circuits throughout the A/D

• Wide Input Common-Mode Voltage Range

converter to provide excellent common-mode signal

• Operating Temperature Range of −40°C to

rejection. The ADC141S626 features an external

+85°C

reference that can be varied from 1.0V to V

. It also

features a zero-power track mode where the ADC is

• SPI™/QSPI™/MICROWIRE/DSP Compatible

consuming the minimum amount of supply current

Serial Interface

while the internal sampling capacitor is tracking the

applied analog input voltage.

APPLICATIONS

The serial data output is binary 2's complement and

• Automotive Navigation

is compatible with several standards, such as SPI™,

• Portable Systems

QSPI™, MICROWIRE, and many common DSP

serial interfaces. The conversion result is clocked out

• Medical Instruments

by the serial clock input and is the result of the

• Instrumentation and Control Systems

conversion currently in progress; thus, ADC141S626

• Motor Control

has no latency.

• Direct Sensor Interface

The ADC141S626 may be operated with independent

analog (V

) and digital input/output (V

) supplies. V

KEY SPECIFICATIONS

and V

can range from 2.7V to 5.5V and can be set

independent of each other. This allows a user to

• Conversion Rate: 50 kSPS to 250 kSPS

maximize performance and minimize power

• INL: ± 0.95 LSB (Max)

consumption by operating the analog portion of the

• DNL: ± 0.95 LSB (Max)

ADC at a V

of 5V while communicating with a 3V

• SNR: 82 dBc (Max)

controller on the digital side. With a 3V source, the

power consumption when operating at 200 kSPS is

• THD: -90 dBc (Typ)

2.0 mW. With a 5V source, the power consumption

• ENOB: 13.3 Bits(Min)

when operating at 250 kSPS is 4.8 mW. The power

• Power Consumption:

consumption drops down to 4 µW and 13 µW

respectively when the ADC141S626 enters

– 200 kSPS, 3V: 2.0 mW (Typ)

acquisition (power-down) mode. The differential input,

– 250 kSPS, 5V: 4.8 mW (Typ)

low power consumption, and small size make the

– Power-Down, 3V: 4 µW (Typ)

ADC141S626 ideal for direct connection to bridge

sensors and transducers in battery operated systems

– Power-Down, 5V: 13 µW (Typ)

or remote data acquisition applications.

Operation is guaranteed over the temperature range

of −40°C to +85°C and clock rates of 0.9 MHz to 4.5

MHz. The ADC141S626 is available in a 10-lead

VSSOP package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

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ADC141S626 www.ti.
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ADC141S626 SNAS434B – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com Connection Diagram VREF 1 10 VA +IN 2 9 VIO - IN 3 ADC141S626 8 SCLK GND 4 7 DOUT GND 5 6 CS Block Diagram SAR CONTROL VREF SERIAL INTERFACE +IN S/H CDAC -IN COMPARATOR PIN DESCRIPTIONS Pin No. Symbol Description 1 VREF Voltage Reference Input. A voltage reference between 1V and VA must be applied to this input. VREF must be decoupled to GND with a minimum ceramic capacitor value of 0.1 µF.
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ADC141S626 www.ti.com SNAS434B – NOVEMBER 2007 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) (3) −0.3V to 6.5V Analog Supply Voltage VA −0.3V to 6.5V Digital I/O Supply Voltage VIO Voltage on Any Analog Input Pin to GND −0.3V to (VA + 0.3V) Voltage on Any Digital Input Pin to GND −0.3V to (VIO + 0.
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ADC141S626 SNAS434B – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com ADC141S626 Converter Electrical Characteristics (1) The following specifications apply for VA = VIO = VREF = +2.7V to 5.5V and fSCLK = 0.9 to 3.6 MHz or VA = VIO = VREF = +4.5V to 5.5V and fSCLK = 3.6 to 4.5 MHz; fIN = 20 kHz and CL = 25 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX; all other limits are at TA = 25°C.
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ADC141S626 www.ti.com SNAS434B – NOVEMBER 2007 – REVISED MARCH 2013 ADC141S626 Converter Electrical Characteristics(1) (continued) The following specifications apply for VA = VIO = VREF = +2.7V to 5.5V and fSCLK = 0.9 to 3.6 MHz or VA = VIO = VREF = +4.5V to 5.5V and fSCLK = 3.6 to 4.5 MHz; fIN = 20 kHz and CL = 25 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX; all other limits are at TA = 25°C. Symbol Parameter Conditions Typical Limits Units 2.7 V (min) 5.
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ADC141S626 SNAS434B – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com ADC141S626 Timing Specifications (1) The following specifications apply for VA = VIO = VREF= +2.7V to 5.5V and fSCLK = 0.9 to 4.5 MHz, CL = 25 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
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ADC141S626 www.ti.com SNAS434B – NOVEMBER 2007 – REVISED MARCH 2013 0.9 x VIO DOUT CS 0.1 x VIO tr VIH tf 90% 90% DOUT 10% tDIS 90% DOUT 10% 10% Figure 4. DOUT Rise and Fall Times Figure 5. Voltage Waveform for tDIS SCLK VIL tDA 2.3V DOUT 0.7V tDH Figure 6. DOUT Hold and Access Times Specification Definitions APERTURE DELAY is the time between the first falling edge of SCLK and the time when the input signal is sampled for conversion.
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ADC141S626 SNAS434B – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com POSITIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output code transitions to positive full scale and VREF minus 1 LSB. POSITIVE GAIN ERROR is the difference between the positive full-scale error and the offset error. POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well a change in the analog supply voltage is rejected.
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ADC141S626 www.ti.com SNAS434B – NOVEMBER 2007 – REVISED MARCH 2013 Typical Performance Characteristics VA = VIO = VREF = +5V, fSCLK = 4.5 MHz, fSAMPLE = 250 kSPS, TA = +25°C, and fIN = 20 kHz unless otherwise stated. DNL - 250 kSPS INL - 250 kSPS Figure 7. Figure 8. DNL vs. VA INL vs. VA Figure 9. Figure 10. DNL vs. VREF INL vs. VREF Figure 11. Figure 12.
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ADC141S626 SNAS434B – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VA = VIO = VREF = +5V, fSCLK = 4.5 MHz, fSAMPLE = 250 kSPS, TA = +25°C, and fIN = 20 kHz unless otherwise stated. 10 DNL vs. SCLK FREQUENCY INL vs. SCLK FREQUENCY Figure 13. Figure 14. DNL vs. TEMPERATURE INL vs. TEMPERATURE Figure 15. Figure 16. SINAD vs. VA THD vs. VA Figure 17. Figure 18.
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ADC141S626 www.ti.com SNAS434B – NOVEMBER 2007 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VA = VIO = VREF = +5V, fSCLK = 4.5 MHz, fSAMPLE = 250 kSPS, TA = +25°C, and fIN = 20 kHz unless otherwise stated. SINAD vs. VREF THD vs. VREF Figure 19. Figure 20. SINAD vs. SCLK FREQUENCY THD vs. SCLK FREQUENCY Figure 21. Figure 22. SINAD vs. INPUT FREQUENCY THD vs. INPUT FREQUENCY Figure 23. Figure 24.
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ADC141S626 SNAS434B – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VA = VIO = VREF = +5V, fSCLK = 4.5 MHz, fSAMPLE = 250 kSPS, TA = +25°C, and fIN = 20 kHz unless otherwise stated. 12 SINAD vs. TEMPERATURE THD vs. TEMPERATURE Figure 25. Figure 26. VA CURRENT vs. VA VA CURRENT vs. SCLK FREQUENCY Figure 27. Figure 28. VA CURRENT vs. TEMPERATURE VREF CURRENT vs. VREF Figure 29. Figure 30.
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ADC141S626 www.ti.com SNAS434B – NOVEMBER 2007 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VA = VIO = VREF = +5V, fSCLK = 4.5 MHz, fSAMPLE = 250 kSPS, TA = +25°C, and fIN = 20 kHz unless otherwise stated. VREF CURRENT vs. SCLK FREQUENCY VREF CURRENT vs. TEMPERATURE Figure 31. Figure 32. VIO CURRENT vs. VIO VIO CURRENT vs. SCLK FREQUENCY Figure 33. Figure 34. VIO CURRENT vs. TEMPERATURE SPECTRAL RESPONSE - 250 kSPS Figure 35. Figure 36.
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ADC141S626 SNAS434B – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com FUNCTIONAL DESCRIPTION The ADC141S626 is a 14-bit, 50 kSPS to 250 kSPS sampling Analog-to-Digital (A/D) converter. The converter uses a successive approximation register (SAR) architecture based upon capacitive redistribution containing an inherent sample-and-hold function.
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ADC141S626 www.ti.com SNAS434B – NOVEMBER 2007 – REVISED MARCH 2013 ANALOG SIGNAL INPUTS The ADC141S626 has a differential input where the effective input voltage that is digitized is (+IN) − (−IN). By using this differential input, small signals common to both inputs are rejected. As shown in Figure 37, noise is immune at low frequencies where the common-mode rejection ratio (CMRR) is 90 dB. As the frequency increases to 1 MHz, the CMRR rolls off to 40 dB .
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ADC141S626 SNAS434B – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com VREF 2 VCM VCM + RS VCM VREF 2 - VREF SRC + CS RS ADC141S626 - VREF 2 VCM VCM + VCM - VREF 2 Figure 39. Differential Input Single-Ended Input Operation For single-ended operation, the non-inverting input (+IN) of the ADC141S626 can be driven with a signal that has a peak-to-peak range that is equal to or less than (2 x VREF).
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ADC141S626 www.ti.com SNAS434B – NOVEMBER 2007 – REVISED MARCH 2013 Table 1. Allowable VCM Range Input Signal Differential Single-Ended Minimum VCM Maximum VCM VREF / 2 VA − VREF / 2 VREF VA − VREF SERIAL DIGITAL INTERFACE The ADC141S626 communicates via a synchronous 3-wire serial interface as shown in Figure 1 or re-shown in Figure 43 for convenience. CS, chip select bar, initiates conversions and frames the serial data transfers.
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ADC141S626 SNAS434B – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com Data Output The data output format of the ADC141S626 is two’s complement as shown in Figure 38. This figure indicates the ideal output code for a given input voltage and does not include the effects of offset, gain error, linearity errors, or noise. Each data output bit is output on the falling edges of SCLK.
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ADC141S626 www.ti.com SNAS434B – NOVEMBER 2007 – REVISED MARCH 2013 Burst Mode Operation Normal operation of the ADC141S626 requires the SCLK frequency to be 18 times the sample rate and the CS rate to be the same as the sample rate. However, in order to minimize power consumption in applications requiring sample rates below 250 kSPS, the ADC141S626 should be run with an SCLK frequency of 4.5 MHz and a CS rate as slow as the system requires.
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ADC141S626 SNAS434B – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. However, to maximize accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. In addition, the clock line should also be treated as a transmission line and be properly terminated.
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ADC141S626 www.ti.com SNAS434B – NOVEMBER 2007 – REVISED MARCH 2013 APPLICATION CIRCUITS The following figures are examples of the ADC141S626 in typical application circuits. These circuits are basic and will generally require modification for specific circumstances. Data Acquisition Figure 44 shows a typical connection diagram for the ADC141S626 operating at VA of +5V. VREF is connected to a 4.1V shunt reference, the LM4040-4.
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ADC141S626 SNAS434B – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com Current Sensing Application Figure 46 shows an example of interfacing a current transducer to the ADC141S626. The current transducer converts an input current into a voltage that is converted by the ADC. Since the output voltage of the current transducer is single-ended and centered around a common-mode voltage (VCM) of 2.
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ADC141S626 www.ti.com SNAS434B – NOVEMBER 2007 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision A (March 2013) to Revision B • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 21-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADC141S626CIMM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADC141S626CIMMX/NOP VSSOP B DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 21-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC141S626CIMM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 VSSOP DGS 10 3500 367.0 367.0 35.
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