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ADC161S626

www.ti.com

SNAS468C –SEPTEMBER 2008–REVISED MARCH 2013

ADC161S626 16-Bit, 50 to 250 kSPS, Differential Input, MicroPower ADC

Check for Samples: ADC161S626

FEATURES

KEY SPECIFICATIONS

• 16-bit Resolution with No Missing Codes

• Conversion Rate 50 to 250 kSPS

• Ensured Performance from 50 to 250 kSPS • DNL + 0.8 / − 0.5 LSB

• ±0.003% Signal Span Accuracy • INL ± 0.8 LSB

• Separate Digital Input/Output Supply • Offset Error Temp Drift 2.5 μV/°C

• True Differential Input • Gain Error Temp Drift 0.3 ppm/°C

• External Voltage Reference Range of +0.5V to • SNR 93.2 dBc

• THD − 104 dBc

• Zero-Power Track Mode with 0 µsec Wake-up

• Power Consumption

Delay

– 10 kSPS, 5V 0.24 mW

• Wide Input Common-mode Voltage Range of

– 200 kSPS, 5V 5.3 mW

0V to V

– 250 kSPS, 5V 5.8 mW

• SPI™/QSPI™/MICROWIRE™ Compatible Serial

– Power-Down, 5V 10 μW

Interface

• Operating Temperature Range of −40°C to

DESCRIPTION

+85°C

The ADC161S626 is a 16-bit successive-

• Small VSSOP-10 Package

approximation register (SAR) Analog-to-Digital

converter (ADC) with a maximum sampling rate of

APPLICATIONS

250 kSPS. The ADC161S626 has a minimum signal

span accuracy of ± 0.003% over the temperate range

• Direct Sensor Interface

of −40°C to +85°C. The converter features a

• I/O Modules

differential analog input with an excellent common-

mode signal rejection ratio of 85 dB, making the

• Data Acquisition

ADC161S626 suitable for noisy environments.

• Portable Systems

The ADC161S626 operates with a single analog

• Motor Control

supply (V

) and a separate digital input/output (V

)

• Medical Instruments

supply. V

can range from +4.5V to +5.5V and V

• Instrumentation and Control Systems

can range from +2.7V to +5.5V. This allows a system

designer to maximize performance and minimize

power consumption by operating the analog portion of

the ADC at a V

of +5V while interfacing with a +3.3V

controller. The serial data output is binary 2's

complement and is SPI™ compatible.

The performance of the ADC161S626 is ensured

over temperature at clock rates of 1 MHz to 5 MHz

and reference voltages of +2.5V to +5.5V. The

ADC161S626 is available in a small 10-lead VSSOP

package. The high accuracy, differential input, low

power consumption, and small size make the

ADC161S626 ideal for direct connection to bridge

sensors and transducers in battery operated systems

or remote data acquisition applications.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (30 pages)

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ADC161S626 www.ti.com SNAS468C – SEPTEMBER 2008 – REVISED MARCH 2013 ADC161S626 16-Bit, 50 to 250 kSPS, Differential Input, MicroPower ADC Check for Samples: ADC161S626 FEATURES KEY SPECIFICATIONS • • • • • • • • • • • • • • 1 2 • • • • • 16-bit Resolution with No Missing Codes Ensured Performance from 50 to 250 kSPS ±0.003% Signal Span Accuracy Separate Digital Input/Output Supply True Differential Input External Voltage Reference Range of +0.
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ADC161S626 SNAS468C – SEPTEMBER 2008 – REVISED MARCH 2013 www.ti.com Typical Application VBRIDGE +3.3V +5V + SCLK + VA VIO - DOUT ADC161S626 - VREF CSB MicroController LM4120-2.5 + 4.7 PF 0.1 PF +5V Block Diagram SAR CONTROL VREF SERIAL INTERFACE +IN S/H CDAC -IN COMPARATOR Connection Diagram VREF 1 10 VA +IN 2 9 VIO - IN 3 ADC161S626 8 SCLK GND 4 7 DOUT GND 5 6 CS Figure 1. VSSOP Package See Package Number DGS0010A Pin Descriptions Pin No.
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ADC161S626 www.ti.com SNAS468C – SEPTEMBER 2008 – REVISED MARCH 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) −0.3V to 6.5V Analog Supply Voltage VA −0.3V to 6.5V Digital I/O Supply Voltage VIO Voltage on Any Analog Input Pin to GND −0.3V to (VA + 0.3V) Voltage on Any Digital Input Pin to GND −0.
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ADC161S626 SNAS468C – SEPTEMBER 2008 – REVISED MARCH 2013 www.ti.com Package Thermal Resistance Package θJA 10-lead VSSOP 240°C / W Soldering process must comply with Reflow Temperature Profile specifications. Refer to http://www.ti.com/packaging. (1) (1) Reflow temperature profiles are different for lead-free packages. ADC161S626 Converter Electrical Characteristics (1) The following specifications apply for VA = 4.5V to 5.5V, VIO = 2.7V to 5.5V, and VREF = 2.5V to 5.
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ADC161S626 www.ti.com SNAS468C – SEPTEMBER 2008 – REVISED MARCH 2013 ADC161S626 Converter Electrical Characteristics (1) (continued) The following specifications apply for VA = 4.5V to 5.5V, VIO = 2.7V to 5.5V, and VREF = 2.5V to 5.5V for fSCLK = 1 MHz to 4 MHz or VREF = 4.5V to 5.5V for fSCLK = 1 MHz to 5 MHz; fIN = 20 kHz, and CL = 25 pF, unless otherwise noted. Maximum and minimum values apply for TA = TMIN to TMAX; the typical values are tested at TA = 25°C. Parameter Typ Max 1.7 0.
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ADC161S626 SNAS468C – SEPTEMBER 2008 – REVISED MARCH 2013 www.ti.com ADC161S626 Converter Electrical Characteristics (1) (continued) The following specifications apply for VA = 4.5V to 5.5V, VIO = 2.7V to 5.5V, and VREF = 2.5V to 5.5V for fSCLK = 1 MHz to 4 MHz or VREF = 4.5V to 5.5V for fSCLK = 1 MHz to 5 MHz; fIN = 20 kHz, and CL = 25 pF, unless otherwise noted. Maximum and minimum values apply for TA = TMIN to TMAX; the typical values are tested at TA = 25°C.
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ADC161S626 www.ti.com SNAS468C – SEPTEMBER 2008 – REVISED MARCH 2013 (1) ADC161S626 Timing Specifications The following specifications apply for VA = 4.5V to 5.5V, VIO = 2.7V to 5.5V, VREF = 2.5V to 5.5V, fSCLK = 1Mz to 5MHz, and CL = 25 pF, unless otherwise noted. Maximum and minimum values apply for TA = TMIN to TMAX; the typical values are tested at TA = 25°C.
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ADC161S626 SNAS468C – SEPTEMBER 2008 – REVISED MARCH 2013 www.ti.com SCLK VIL tDA 0.7 x VIO DOUT 0.3 x VIO tDH Figure 5. DOUT Hold and Access Times SCLK 1 2 tCSH tCSS CS Figure 6. Valid CS Assertion Times CS VIH 90% 90% DOUT 10% tDIS 90% DOUT 10% 10% Figure 7. Voltage Waveform for tDIS Specification Definitions APERTURE DELAY is the time between the first falling edge of SCLK and the time when the input signal is sampled for conversion.
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ADC161S626 www.ti.com SNAS468C – SEPTEMBER 2008 – REVISED MARCH 2013 INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from ½ LSB below the first code transition through ½ LSB above the last code transition. The deviation of any given code from this straight line is measured from the center of that code value. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC161S626 is ensured not to have any missing codes.
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ADC161S626 SNAS468C – SEPTEMBER 2008 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics VA = VIO = VREF = +5V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = +25°C, and fIN = 20 kHz unless otherwise stated. 10 DNL - 250 kSPS INL - 250 kSPS Figure 8. Figure 9. DNL vs. VA INL vs. VA Figure 10. Figure 11. DNL vs. VREF INL vs. VREF Figure 12. Figure 13.
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ADC161S626 www.ti.com SNAS468C – SEPTEMBER 2008 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VA = VIO = VREF = +5V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = +25°C, and fIN = 20 kHz unless otherwise stated. DNL vs. SCLK FREQUENCY INL vs. SCLK FREQUENCY Figure 14. Figure 15. DNL vs. TEMPERATURE INL vs. TEMPERATURE Figure 16. Figure 17. SINAD vs. VA THD vs. VA Figure 18. Figure 19.
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ADC161S626 SNAS468C – SEPTEMBER 2008 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VA = VIO = VREF = +5V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = +25°C, and fIN = 20 kHz unless otherwise stated. 12 SINAD vs. VREF THD vs. VREF Figure 20. Figure 21. SINAD vs. SCLK FREQUENCY THD vs. SCLK FREQUENCY Figure 22. Figure 23. SINAD vs. INPUT FREQUENCY THD vs. INPUT FREQUENCY Figure 24. Figure 25.
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ADC161S626 www.ti.com SNAS468C – SEPTEMBER 2008 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VA = VIO = VREF = +5V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = +25°C, and fIN = 20 kHz unless otherwise stated. SINAD vs. TEMPERATURE THD vs. TEMPERATURE Figure 26. Figure 27. VA CURRENT vs. VA VA CURRENT vs. SCLK FREQUENCY Figure 28. Figure 29. VA CURRENT vs. TEMPERATURE VREF CURRENT vs. VREF Figure 30. Figure 31.
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ADC161S626 SNAS468C – SEPTEMBER 2008 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VA = VIO = VREF = +5V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = +25°C, and fIN = 20 kHz unless otherwise stated. 14 VREF CURRENT vs. SCLK FREQUENCY VREF CURRENT vs. TEMPERATURE Figure 32. Figure 33. VIO CURRENT vs. VIO VIO CURRENT vs. SCLK FREQUENCY Figure 34. Figure 35. VIO CURRENT vs. TEMPERATURE SPECTRAL RESPONSE - 250 kSPS Figure . Figure 36.
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ADC161S626 www.ti.com SNAS468C – SEPTEMBER 2008 – REVISED MARCH 2013 FUNCTIONAL DESCRIPTION The ADC161S626 is a 16-bit, 50 kSPS to 250 kSPS sampling Analog-to-Digital (A/D) converter. The converter uses a successive approximation register (SAR) architecture based upon capacitive redistribution containing an inherent sample-and-hold function.
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ADC161S626 SNAS468C – SEPTEMBER 2008 – REVISED MARCH 2013 www.ti.com Differential Input Operation The transfer curve of the ADC161S626 for a fully differential input signal is shown in Figure 37. A positive full scale output code (0111 1111 1111 1111b or 7FFFh or 32,767d) will be obtained when (+IN) − (−IN) is greater than or equal to (VREF − 1 LSB). A negative full scale code (1000 0000 0000 0000b or 8000h or -32,768d) will be obtained when [(+IN) − (−IN)] is less than or equal to (−VREF + 1 LSB).
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ADC161S626 www.ti.com SNAS468C – SEPTEMBER 2008 – REVISED MARCH 2013 Since the design of the ADC161S626 is optimized for a differential input, the performance degrades slightly when driven with a single-ended input. Linearity characteristics such as INL and DNL typically degrade by 0.1 LSB and dynamic characteristics such as SINAD typically degrade by 2 dB. Note that single-ended operation should only be used if the performance degradation (compared with differential operation) is acceptable.
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ADC161S626 SNAS468C – SEPTEMBER 2008 – REVISED MARCH 2013 www.ti.com Figure 42. Analog Input CMRR vs. Frequency Noise The noise floor of the ADC161S626 is very low as shown in Figure 43 and Figure 44. These figures were created by driving the ADC input with a low-noise voltage source set near 0V. For Figure 43, the input was adjusted in order to obtain the code 0x0000h. For Figure 44, the input was increased by 1/2 LSB in order to obtain the transition point between code 0x0000h and 0x0001h.
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ADC161S626 www.ti.com SNAS468C – SEPTEMBER 2008 – REVISED MARCH 2013 Input Settling When the ADC161S626 enters acquisition (tACQ) mode at the end of the conversion window, the internal sampling capacitor (CSAMPLE) is connected to the ADC input via an internal switch and a series resistor (RSAMPLE), as shown in Figure 45. Typical values for CSAMPLE and RSAMPLE are 20 pF and 200 ohms respectively.
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ADC161S626 SNAS468C – SEPTEMBER 2008 – REVISED MARCH 2013 www.ti.com SCLK Input The SCLK (serial clock) is used as the conversion clock to shift out the conversion result. SCLK is CMOS compatible. Internal settling time requirements limit the maximum clock frequency while internal capacitor leakage limits the minimum clock frequency. The ADC161S626 offers ensured performance with the clock rates indicated in the electrical table.
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ADC161S626 www.ti.com SNAS468C – SEPTEMBER 2008 – REVISED MARCH 2013 APPLICATIONS INFORMATION OPERATING CONDITIONS We recommend that the following conditions be observed for operation of the ADC161S626: −40°C ≤ TA ≤ +85°C +4.5V ≤ VA ≤ +5.5V +2.7V ≤ VIO ≤ +5.5V +0.5V ≤ VREF ≤ +5.
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ADC161S626 SNAS468C – SEPTEMBER 2008 – REVISED MARCH 2013 www.ti.com Burst Mode Operation Normal operation of the ADC161S626 requires the SCLK frequency to be 20 times the sample rate and the CS rate to be the same as the sample rate. However, in order to minimize power consumption in applications requiring sample rates below 250 kSPS, the ADC161S626 should be run with an SCLK frequency of 5 MHz and a CS rate as slow as the system requires.
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ADC161S626 www.ti.com SNAS468C – SEPTEMBER 2008 – REVISED MARCH 2013 Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. However, to maximize accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. In addition, the clock line should also be treated as a transmission line and be properly terminated.
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ADC161S626 SNAS468C – SEPTEMBER 2008 – REVISED MARCH 2013 www.ti.com A separate power supply (VBR) is assumed to be biasing the bridge sensor but another option for biasing the bridge sensor would be powering it from the +5V power supply. This option has the benefit of providing the ideal common-mode input voltage for the ADC161S626, while keeping design complexity and cost to a minimum. However, any fluctuation in the +5V supply will still be visible on the differential input to the amplification stage.
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ADC161S626 www.ti.com SNAS468C – SEPTEMBER 2008 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision B (March 2013) to Revision C • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADC161S626CIMM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADC161S626CIMME/NOP VSSOP B DGS 10 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADC161S626CIMMX/NOP VSSOP B DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC161S626CIMM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 ADC161S626CIMME/NOP B VSSOP DGS 10 250 210.0 185.0 35.0 ADC161S626CIMMX/NOP B VSSOP DGS 10 3500 367.0 367.0 35.
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