Datasheet

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 Copyright 2011 National Semiconductor Corporation
4.0 Reference Board Functional Description
4.1 System Block Diagram
Figure 17: ADC12D1X00RFRB System Block Diagram
ADC12D1X00RF
Clk Gen
(LMX2531)
USB
Ctrlr.
USB
Xilinx
Virtex
-
4
FPGA
Power Management
12x2
12x2
Ext Clock
DCLK_RST
VinI+/
-
VinQ+/
-
SE2DIFF
Analog_3.3V
Digital_3.3V
Analog_1.9V
7.5V
EEPROM
Local Clock
(96 MHz)
DCLKI/Q
SPI(1.8V)
USI
-
1 Conx.x2 for
external devices
Vcmo
Analog Front
-
End
Boards Plug
-
in Here
(LMH6518, Balun, RF)
D
igital_2.5V
Digital_1.8V
Digital_1.2V
+3.3V/5V,
GND
Analog_3.3/5.0V
(for off
-
board use)
Vreg
+5V
+3.3V
Power
Sequencing
Control
Temp Sensor
(LM95233)
I2C
ADR/DATA
FIFO I/F
uWire
SPI(3.3V)
SE2DIFF
Trigger
SE2DIFF
ORI/Q
2
2