Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal VQFN 32

Input

Mux

3rdOrder

Modulator

REFP REFN

PGA

Burnout

Detect

Burnout

Detect

DVDD

DGND

ADS1146

AVSS

AIN0

AIN1

SCLK

DIN

DRDY

DOUT/DRDY

START

RESET

AVDD

InternalOscillator

Adjustable

Digital

Filter

Serial

Interface

and

Control

CLK

Input

Mux

3rdOrder

Modulator

REFP1 REFN1 VREFOUT VREFCOM

REFP0/

GPIO0

REFN0/

GPIO1

Burnout

Detect

Burnout

Detect

DVDD

DGND

IEXC1AVSS

AIN0/IEXC

AIN1/IEXC

AIN2/IEXC/GPIO2

AIN3/IEXC/GPIO3

AIN4/IEXC/GPIO4

AIN5/IEXC/GPIO5

AIN6/IEXC/GPIO6

AIN7/IEXC/GPIO7

ADS1148 Only

SCLK

DIN

DRDY

DOUT/DRDY

START

RESET

AVDD

IEXC2

InternalOscillator

Voltage

Reference

Serial

Interface

and

Control

BIAS

GPIO

CLK

ADS1148 Only

ADS1147

ADS1148

PGA

System

Monitor

Adjustable

Digital

Filter

Dual

Current

DACs

VREFMux

ADS1148 Only

BIAS

ADS1146

ADS1147

ADS1148

www.ti.com

SBAS453F –JULY 2009–REVISED APRIL 2012

16-Bit Analog-to-Digital Converters for Temperature Sensors

Check for Samples: ADS1146, ADS1147, ADS1148

FEATURES

DESCRIPTION

The ADS1146, ADS1147, and ADS1148 are highly-

• 16 Bits, No Missing Codes

integrated, precision, 16-bit analog-to-digital

• Data Output Rates Up to 2kSPS

converters (ADCs). The ADS1146/7/8 feature an

• Single-Cycle Settling for All Data Rates

onboard, low-noise, programmable gain amplifier

(PGA), a precision delta-sigma ADC with a single-

• Simultaneous 50/60Hz Rejection at 20SPS

cycle settling digital filter, and an internal oscillator.

• 4 Differential/7 Single-Ended Inputs (ADS1148)

The ADS1147 and ADS1148 also provide a built-in

• 2 Differential/3 Single-Ended Inputs (ADS1147)

voltage reference with 10mA output capacity, and two

matched programmable current digital-to-analog

• Matched Current Source DACs

converters (DACs). The ADS1146/7/8 provide a

• Internal Voltage Reference

complete front-end solution for temperature sensor

• Sensor Burnout Detection

applications including thermal couples, thermistors,

and resistance temperature detectors (RTDs).

• 4/8 General-Purpose I/Os (ADS1147/8)

• Internal Temperature Sensor

An input multiplexer supports four differential inputs

for the ADS1148, two for the ADS1147, and one for

• Power Supply and V

REF

Monitoring

the ADS1146. In addition, the multiplexer has a

(ADS1147/8)

sensor burnout detect, voltage bias for

• Self and System Calibration

thermocouples, system monitoring, and general-

• SPI™-Compatible Serial Interface

purpose digital I/Os (ADS1147 and ADS1148). The

onboard, low-noise PGA provides selectable gains of

• Analog Supply Operation:

1 to 128. The delta-sigma modulator and adjustable

+2.7V to +5.25V Unipolar, ±2.5V Bipolar

digital filter settle in only one cycle, for fast channel

• Digital Supply: +2.7V to +5.25V

cycling when using the input multiplexer, and support

• Operating Temperature –40°C to +125°C

data rates up to 2kSPS. For data rates of 20SPS or

less, both 50Hz and 60Hz interference are rejected

by the filter.

APPLICATIONS

• Temperature Measurement

The ADS1146 is offered in a small TSSOP-16

package, the ADS1147 is available in a TSSOP-20

– RTDs, Thermocouples, and Thermistors

package, and the ADS1148 is available in TSSOP-28

• Pressure Measurement

and QFN-32 packages. All three devices operate over

• Industrial Process Control

the extended specified temperature range of –40°C to

+105°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SPI is a trademark of Motorola, Inc.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (66 pages)

PAGE 1
ADS1146 ADS1147 ADS1148 www.ti.com SBAS453F – JULY 2009 – REVISED APRIL 2012 16-Bit Analog-to-Digital Converters for Temperature Sensors Check for Samples: ADS1146, ADS1147, ADS1148 FEATURES DESCRIPTION • • • • • • • • • • • • The ADS1146, ADS1147, and ADS1148 are highlyintegrated, precision, 16-bit analog-to-digital converters (ADCs).
PAGE 2
ADS1146 ADS1147 ADS1148 SBAS453F – JULY 2009 – REVISED APRIL 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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ADS1146 ADS1147 ADS1148 www.ti.com SBAS453F – JULY 2009 – REVISED APRIL 2012 ELECTRICAL CHARACTERISTICS Minimum/maximum specifications apply from –40°C to +105°C. Typical specifications are at +25°C. All specifications at AVDD = +5V, DVDD = +3.3V, AVSS = DGND = 0V, VREF = +2.048V, and oscillator frequency = 4.096MHz, unless otherwise noted.
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ADS1146 ADS1147 ADS1148 SBAS453F – JULY 2009 – REVISED APRIL 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum/maximum specifications apply from –40°C to +105°C. Typical specifications are at +25°C. All specifications at AVDD = +5V, DVDD = +3.3V, AVSS = DGND = 0V, VREF = +2.048V, and oscillator frequency = 4.096MHz, unless otherwise noted.
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ADS1146 ADS1147 ADS1148 www.ti.com SBAS453F – JULY 2009 – REVISED APRIL 2012 THERMAL INFORMATION ADS1146, ADS1147, ADS1148 THERMAL METRIC (1) UNITS PW 28 θJA Junction-to-ambient thermal resistance (2) θJC(top) Junction-to-case(top) thermal resistance 79.5 (3) 31.
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ADS1146 ADS1147 ADS1148 SBAS453F – JULY 2009 – REVISED APRIL 2012 www.ti.
PAGE 7
ADS1146 ADS1147 ADS1148 www.ti.com SBAS453F – JULY 2009 – REVISED APRIL 2012 ADS1148 (QFN-32) PIN DESCRIPTIONS NAME PIN NO.
PAGE 8
ADS1146 ADS1147 ADS1148 SBAS453F – JULY 2009 – REVISED APRIL 2012 www.ti.com PW PACKAGE TSSOP-16 (TOP VIEW) DVDD 1 16 SCLK DGND 2 15 DIN CLK 3 14 DOUT/DRDY RESET 4 13 DRDY ADS1146 REFP 5 12 CS REFN 6 11 START AINP 7 10 AVDD AINN 8 9 AVSS ADS1146 (TSSOP-16) PIN DESCRIPTIONS NAME PIN NO. FUNCTION DVDD 1 Digital Digital power supply DGND 2 Digital Digital ground CLK 3 Digital input External clock input. Tie this pin to DGND to activate the internal oscillator.
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ADS1146 ADS1147 ADS1148 www.ti.com SBAS453F – JULY 2009 – REVISED APRIL 2012 PW PACKAGE TSSOP-20 (TOP VIEW) DVDD 1 20 SCLK DGND 2 19 DIN CLK 3 18 DOUT/DRDY RESET 4 17 DRDY REFP0/GPIO0 5 16 CS ADS1147 REFN0/GPIO1 6 15 START VREFOUT 7 14 AVDD VREFCOM 8 13 AVSS AIN0/IEXC 9 12 AIN3/IEXC/GPIO3 AIN1/IEXC 10 11 AIN2/IEXC/GPIO2 ADS1147 (TSSOP-20) PIN DESCRIPTIONS NAME PIN NO.
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ADS1146 ADS1147 ADS1148 SBAS453F – JULY 2009 – REVISED APRIL 2012 www.ti.
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ADS1146 ADS1147 ADS1148 www.ti.com SBAS453F – JULY 2009 – REVISED APRIL 2012 ADS1148 (TSSOP-28) PIN DESCRIPTIONS NAME PIN NO. FUNCTION DVDD 1 Digital Digital power supply DESCRIPTION DGND 2 Digital Digital ground CLK 3 Digital input External clock input. Tie this pin to DGND to activate the internal oscillator. RESET 4 Digital input Chip reset (active low). Returns all register values to reset values.
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ADS1146 ADS1147 ADS1148 SBAS453F – JULY 2009 – REVISED APRIL 2012 www.ti.com TIMING DIAGRAMS tCSPW CS tCSSC tSPWH tSCLK tSCCS SCLK DIN DIN[0] tSPWL tDIHD tDIST DIN[7] DIN[6] DIN[5] DOUT[7] DOUT[6] DOUT[5] DIN[4] DIN[1] tDOPD DOUT/DRDY (1) DIN[0] tDOHD DOUT[4] DOUT[1] DOUT[0] tCSDO Figure 1.
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ADS1146 ADS1147 ADS1148 www.ti.com SBAS453F – JULY 2009 – REVISED APRIL 2012 tSTART START Figure 3. Minimum START Pulse Width Timing Characteristics for Figure 3 SYMBOL tSTART DESCRIPTION MIN START pulse width high MAX 3 UNIT tOSC tRESET RESET CS SCLK tRHSC Figure 4. Reset Pulse Width and SPI Communication After Reset Timing Characteristics for Figure 4 SYMBOL DESCRIPTION MIN t RESET RESET pulse width low 4 tOSC tRHSC RESET high to SPI communication start 0.
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ADS1146 ADS1147 ADS1148 SBAS453F – JULY 2009 – REVISED APRIL 2012 www.ti.com NOISE PERFORMANCE The ADS1146/7/8 noise performance can be optimized by adjusting the data rate and PGA setting. As the averaging is increased by reducing the data rate, the noise drops correspondingly. Increasing the PGA value reduces the input-referred noise, particularly useful when measuring low-level signals. Table 1 and Table 2 summarize noise performance of the ADS1146/7/8.
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ADS1146 ADS1147 ADS1148 www.ti.com SBAS453F – JULY 2009 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted.
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ADS1146 ADS1147 ADS1148 SBAS453F – JULY 2009 – REVISED APRIL 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted. DATA RATE ERROR vs TEMPERATURE IDAC LINE REGULATION 1.002 2.5 1.001 2.0 1.000 Normalized Output Current 3.0 Data Rate Error (%) 1.5 1.0 DVDD = 5V 0.5 0 DVDD = 3.3V -0.5 -1.0 -1.5 -2.0 0.999 40 60 80 100 750mA 0.994 0.993 0.991 20 250mA 0.995 0.992 0 500mA 0.996 -3.0 -20 100mA 0.997 -2.
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ADS1146 ADS1147 ADS1148 www.ti.com SBAS453F – JULY 2009 – REVISED APRIL 2012 GENERAL DESCRIPTION OVERVIEW The ADS1147 and ADS1148 also include a flexible input multiplexer with system monitoring capability and general-purpose I/O settings, a very low-drift voltage reference, and two matched current sources for sensor excitation. Figure 17 and Figure 18 show the various functions incorporated into each device. The ADS1146, ADS1147 and ADS1148 are highly integrated 24-bit data converters.
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ADS1146 ADS1147 ADS1148 SBAS453F – JULY 2009 – REVISED APRIL 2012 www.ti.com ADC INPUT AND MULTIPLEXER The ADS1146/7/8 ADC measures the input signal through the onboard PGA. All analog inputs are connected to the internal AINP or AINN analog inputs through the analog multiplexer. A block diagram of the analog input multiplexer is shown in Figure 19.
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ADS1146 ADS1147 ADS1148 www.ti.com SBAS453F – JULY 2009 – REVISED APRIL 2012 ESD diodes protect the ADC inputs. To prevent these diodes from turning on, make sure the voltages on the input pins do not go below AVSS by more than 100mV, and do not exceed AVDD by more than 100mV, as shown in Equation 2. Note that the same caution is true if the inputs are configured to be GPIOs.
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ADS1146 ADS1147 ADS1148 SBAS453F – JULY 2009 – REVISED APRIL 2012 www.ti.com LOW-NOISE PGA AVSS + 0.1V + The ADS1146/7/8 feature a low-drift, low-noise, high input impedance programmable gain amplifier (PGA). The PGA can be set to gain of 1, 2, 4, 8, 16, 32, 64, or 128 by register SYS0. A simplified diagram of the PGA is shown in Figure 21. 454W AINP 7.5pF A1 ) ( ) (VIN)(Gain) (V )(Gain) £ VCMI £ AVDD - 0.1V - IN 2 2 (4) MODULATOR A third-order modulator is used in the ADS1146/7/8.
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ADS1146 ADS1147 ADS1148 SBAS453F – JULY 2009 – REVISED APRIL 2012 0 -60 -20 -70 Magnitude (dB) Magnitude (dB) www.ti.com -40 -60 -80 -80 -90 -100 -110 -100 -120 -120 0 20 40 60 80 48 100 120 140 160 180 200 50 Figure 22. Filter Profile with Data Rate = 5SPS 52 54 56 58 60 62 Frequency (Hz) Frequency (Hz) Figure 25.
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ADS1146 ADS1147 ADS1148 www.ti.com 0 0 -20 -20 Magnitude (dB) Magnitude (dB) SBAS453F – JULY 2009 – REVISED APRIL 2012 -40 -60 -80 -100 -40 -60 -80 -100 -120 -120 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 1 2 3 Frequency (Hz) 0 0 -20 -20 -40 -60 -80 -100 6 7 8 9 10 -40 -60 -80 -100 -120 -120 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 0 2 4 Frequency (Hz) Figure 29.
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ADS1146 ADS1147 ADS1148 www.ti.com SBAS453F – JULY 2009 – REVISED APRIL 2012 INTERNAL VOLTAGE REFERENCE The ADS1147 and ADS1148 include an onboard voltage reference with a low temperature coefficient. The output of the voltage reference is 2.048V with the capability of both sourcing and sinking up to 10mA of current. The voltage reference must have a capacitor connected between VREFOUT and VREFCOM. The value of the capacitance should be in the range of 1μF to 47μF.
PAGE 24
ADS1146 ADS1147 ADS1148 SBAS453F – JULY 2009 – REVISED APRIL 2012 www.ti.com GENERAL-PURPOSE DIGITAL I/O Power-Supply Monitor The ADS1148 has eight pins and the ADS1147 has four pins that serve a dual purpose as either analog inputs or general-purpose digital inputs/outputs (GPIOs). The system monitor can measure the analog or digital power supply. When measuring the power supply, the resulting conversion is approximately 1/4 of the actual power supply voltage.
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ADS1146 ADS1147 ADS1148 www.ti.com SBAS453F – JULY 2009 – REVISED APRIL 2012 CALIBRATION The conversion data are scaled by offset and gain registers before yielding the final output code. As shown in Figure 34, the output of the digital filter is first subtracted by the offset register (OFC) and then multiplied by the full-scale register (FSC). A digital clipping circuit ensures that the output code does not exceed 16 bits. Equation 7 shows the scaling.
PAGE 26
ADS1146 ADS1147 ADS1148 SBAS453F – JULY 2009 – REVISED APRIL 2012 www.ti.com Calibration Commands The ADS1146/7/8 provide commands for three types of calibration: system gain calibration, system offset calibration and self offset calibration. Where absolute accuracy is needed, it is recommended that calibration be performed after power on, a change in temperature, a change of PGA and in some cases a change in channel.
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ADS1146 ADS1147 ADS1148 www.ti.com SBAS453F – JULY 2009 – REVISED APRIL 2012 ADC CONTROL down to save power. During shutdown, the conversion result can be retrieved; however, START must be taken high before communicating with the configuration registers. The device stays shut down until the START pin is once again taken high to begin a new conversion.
PAGE 28
ADS1146 ADS1147 ADS1148 SBAS453F – JULY 2009 – REVISED APRIL 2012 www.ti.com The ADS1146/7/8 can be configured to convert continuously by holding the START pin high, as shown in Figure 36. With the START pin held high, the ADC converts the selected input channels continuously. This configuration continues until the START pin is taken low. The START pin can also be used to perform the synchronized measurement for the multi-channel applications by pulsing the START pin.
PAGE 29
ADS1146 ADS1147 ADS1148 www.ti.com SBAS453F – JULY 2009 – REVISED APRIL 2012 Digital Filter Reset Operation Apart from the RESET command and the RESET pin, the digital filter is reset automatically when either a write operation to the MUX0, VBIAS, MUX1, or SYS0 registers is performed, when a SYNC command is issued, or the START pin is taken high. takes place in the VBIAS, MUX1, or SYS0 registers, the filter is reset as well, regardless of whether the value changed or not.
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ADS1146 ADS1147 ADS1148 SBAS453F – JULY 2009 – REVISED APRIL 2012 www.ti.com Data Format The ADS1146/7/8 output 16 bits of data in binary twos complement format. The least significant bit (LSB) has a weight of (VREF/PGA)/(215 – 1). The positive full-scale input produces an output code of 7FFFh and the negative full-scale input produces an output code of 8000h. The output clips at these codes for signals exceeding full-scale. Table 13 summarizes the ideal output codes for different input signals. Table 13.
PAGE 31
ADS1146 ADS1147 ADS1148 www.ti.com SBAS453F – JULY 2009 – REVISED APRIL 2012 DOUT/DRDY This pin has two modes: data out (DOUT) only, or data out (DOUT) combined with data ready (DRDY). The DRDY MODE bit determines the function of this pin. In either mode, the DOUT/DRDY pin goes to a high-impedance state when CS is taken high. by providing 16 SCLKs.
PAGE 32
ADS1146 ADS1147 ADS1148 SBAS453F – JULY 2009 – REVISED APRIL 2012 SCLK DOUT/DRDY(1) DIN www.ti.com 1 2 3 14 D[15] D[14] D[13] D[2] 15 D[1] 16 1 2 8 D[0] NOP 1 2 D[15] D[14] NOP 16 D[0] NOP DRDY (1) DRDY MODE bit enabled, CS tied low. Figure 39. DOUT/DRDY Forced High After Retrieving the Conversion Result 1 2 7 8 1 2 7 8 SCLK DOUT/DRDY(1) reg[7] DIN reg[1] reg[0] NOP NOP (1) DRDY MODE bit enabled, CS tied low. Figure 40.
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ADS1146 ADS1147 ADS1148 www.ti.com SBAS453F – JULY 2009 – REVISED APRIL 2012 REGISTER DESCRIPTIONS ADS1146 REGISTER MAP Table 14.
PAGE 34
ADS1146 ADS1147 ADS1148 SBAS453F – JULY 2009 – REVISED APRIL 2012 www.ti.com ADS1146 DETAILED REGISTER DEFINITIONS (continued) VBIAS—Bias Voltage Register. This register enables a bias voltage on the analog inputs. VBIAS - ADDRESS 01h RESET VALUE = 00h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 0 0 0 0 VBIAS1 VBIAS0 Bits[7:2] These bits must always be set to '000000'.
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ADS1146 ADS1147 ADS1148 www.ti.com SBAS453F – JULY 2009 – REVISED APRIL 2012 ADS1146 DETAILED REGISTER DEFINITIONS (continued) SYS0—System Control Register 0. SYS0 - ADDRESS 03h RESET VALUE = 00h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 PGA2 PGA1 PGA0 DOR3 DOR2 DOR1 DOR0 Bit 7 These bits must always be set to '0'. Bits[6:4] PGA[2:0] These bits determine the gain of the PGA.
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ADS1146 ADS1147 ADS1148 SBAS453F – JULY 2009 – REVISED APRIL 2012 www.ti.com ADS1146 DETAILED REGISTER DEFINITIONS (continued) FSC[23:0] These bits make up the full-scale calibration coefficient register. FSC0—Full-Scale Calibration Coefficient Register 0 RESET VALUE IS PGA DEPENDENT (1) FSC0 - ADDRESS 07h (1) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0 The reset value for FSC is factory-trimmed for each PGA setting.
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ADS1146 ADS1147 ADS1148 www.ti.com SBAS453F – JULY 2009 – REVISED APRIL 2012 ADS1147 AND ADS1148 REGISTER MAP Table 16.
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ADS1146 ADS1147 ADS1148 SBAS453F – JULY 2009 – REVISED APRIL 2012 www.ti.com ADS1147 AND ADS1148 DETAILED REGISTER DEFINITIONS MUX0—Multiplexer Control Register 0. This register allows any combination of differential inputs to be selected on any of the input channels. Note that this setting can be superceded by the MUXCAL and VBIAS bits.
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ADS1146 ADS1147 ADS1148 www.ti.com SBAS453F – JULY 2009 – REVISED APRIL 2012 ADS1147 AND ADS1148 DETAILED REGISTER DEFINITIONS (continued) MUX1—Multiplexer Control Register 1 MUX1 - ADDRESS 02h RESET VALUE = 00h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CLKSTAT VREFCON1 VREFCON0 REFSELT1 REFSELT0 MUXCAL2 MUXCAL1 MUXCAL0 Bit 7 CLKSTAT This bit is read-only and indicates whether the internal or external oscillator is being used.
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ADS1146 ADS1147 ADS1148 SBAS453F – JULY 2009 – REVISED APRIL 2012 www.ti.com ADS1147 AND ADS1148 DETAILED REGISTER DEFINITIONS (continued) SYS0—System Control Register 0 SYS0 - ADDRESS 03h RESET VALUE = 00h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 PGA2 PGA1 PGA0 DOR3 DOR2 DOR1 DOR0 Bit 7 This bit must always be set to '0' Bits[6:4] PGA[2:0] These bits determine the gain of the PGA.
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ADS1146 ADS1147 ADS1148 www.ti.com SBAS453F – JULY 2009 – REVISED APRIL 2012 ADS1147 AND ADS1148 DETAILED REGISTER DEFINITIONS (continued) FSC[23:0] These bits make up the full-scale calibration coefficient register. FSC0—Full-Scale Calibration Coefficient Register 0 RESET VALUE IS PGA DEPENDENT (1) FSC0 - ADDRESS 07h (1) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0 The reset value for FSC is factory-trimmed for each PGA setting.
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ADS1146 ADS1147 ADS1148 SBAS453F – JULY 2009 – REVISED APRIL 2012 www.ti.
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ADS1146 ADS1147 ADS1148 www.ti.com SBAS453F – JULY 2009 – REVISED APRIL 2012 ADS1147 AND ADS1148 DETAILED REGISTER DEFINITIONS (continued) GPIOCFG—GPIO Configuration Register.
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ADS1146 ADS1147 ADS1148 SBAS453F – JULY 2009 – REVISED APRIL 2012 www.ti.com SPI COMMANDS SPI COMMAND DEFINITIONS The commands shown in Table 18 control the operation of the ADS1146/7/8. Some of the commands are standalone commands (for example, RESET), whereas others require additional bytes (for example, WREG requires command, count, and the data bytes). Operands: n = number of registers to be read or written (number of bytes – 1) r = register (0 to 15) x = don't care Table 18.
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ADS1146 ADS1147 ADS1148 www.ti.com SBAS453F – JULY 2009 – REVISED APRIL 2012 SYSTEM CONTROL COMMANDS WAKEUP—Wake up from sleep mode that is set by the SLEEP command. Use this command to awaken the device from sleep mode. After execution of the WAKEUP command, the device wakes up on the rising edge of the eighth SCLK. SLEEP—Set the device to sleep mode; issue the WAKEUP command to deactivate SLEEP mode. This command places the part into a sleep (power-saving) mode.
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ADS1146 ADS1147 ADS1148 SBAS453F – JULY 2009 – REVISED APRIL 2012 www.ti.com DATA RETRIEVAL COMMANDS RDATAC—Read data continuously. The RDATAC command enables the automatic loading of a new conversion result into the output data register. In this mode, the conversion result can be received once from the device after the DRDY signal goes low by sending 16 SCLKs. It is not necessary to read back all the bits, as long as the number of bits read out is a multiple of eight.
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ADS1146 ADS1147 ADS1148 www.ti.com SBAS453F – JULY 2009 – REVISED APRIL 2012 RDATA—Read data once. The RDATA command loads the most recent conversion result into the output register. After issuing this command, the conversion result can be read out by sending 16 SCLKs, as shown in Figure 46. This command also works in RDATAC mode.
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ADS1146 ADS1147 ADS1148 SBAS453F – JULY 2009 – REVISED APRIL 2012 www.ti.com USER REGISTER READ AND WRITE COMMANDS RREG—Read from registers. This command outputs the data from up to 16 registers, starting with the register address specified as part of the instruction. The number of registers read is one plus the second byte. If the count exceeds the remaining registers, the addresses wrap back to the beginning. 1st Command Byte: 0010 rrrr, where rrrr is the address of the first register to read.
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ADS1146 ADS1147 ADS1148 www.ti.com SBAS453F – JULY 2009 – REVISED APRIL 2012 CALIBRATION COMMANDS The ADS1146/7/8 provide system and offset calibration commands and a system gain calibration command. SYSOCAL—Offset system calibration. This command initiates a system offset calibration. For a system offset calibration, the input should be externally set to zero. The OFC register is updated when this operation completes. SYSGCAL—System gain calibration. This command initiates the system gain calibration.
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ADS1146 ADS1147 ADS1148 SBAS453F – JULY 2009 – REVISED APRIL 2012 www.ti.com APPLICATION INFORMATION SPI COMMUNICATION EXAMPLES negative terminal of both sensors (that is, channels AIN1 and AIN3). All these settings can be changed by performing a block write operation on the first four registers of the device. After the DRDY pin goes low, the conversion result can be immediately retrieved by sending in 16 SPI clock pulses because the device defaults to RDATAC mode.
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ADS1146 ADS1147 ADS1148 www.ti.com SBAS453F – JULY 2009 – REVISED APRIL 2012 Sleep Mode Example This second example deals with performing one conversion after power-up and then entering into the power-saving sleep mode. In this example, a sensor is connected to input channels AIN0 and AIN1. Commands to set up the devices must occur at least 216 system clock cycles after powering up the devices. The ADC operates at a data rate of 2kSPS. The PGA gain is set to 32 for both sensors.
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ADS1146 ADS1147 ADS1148 SBAS453F – JULY 2009 – REVISED APRIL 2012 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (April 2012) to Revision F Page • Added QFN-32 to listed packages available for the ADS1148 in Description section ......................................................... 1 • Added ADS1148, QFN-32 row to Package/Ordering Information table ...................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 27-Jul-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 5.6 1.6 8.0 12.0 Q1 ADS1146IPWR TSSOP PW 16 2000 330.0 12.4 6.9 ADS1147IPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 ADS1148IPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1146IPWR TSSOP PW 16 2000 367.0 367.0 35.0 ADS1147IPWR TSSOP PW 20 2000 367.0 367.0 38.0 ADS1148IPWR TSSOP PW 28 2000 367.0 367.0 38.0 ADS1148IRHBR VQFN RHB 32 3000 367.0 367.0 35.0 ADS1148IRHBT VQFN RHB 32 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.