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ADS1174

ADS1178

FEATURES DESCRIPTION

APPLICATIONS

VREFP VREFN AVDD DVDD

TEST[1:0]

FORMAT[2:0]

CLK

SYNC

PWDN[8:1]

CLKDIV

Control

Logic

SPI

and

Frame-

Sync

Interface

IOVDD

DGNDAGND

DRDY/FSYNC

SCLK

DOUT[8:1]

DIN

Input2

Input1

Input4

Input3

Input6

Input5

Input8

Input7

PWDN[4:1]

ADS1178

Four

Digital

Filters

AVDD DVDD

TEST[1:0]

FORMAT[2:0]

CLK

SYNC

CLKDIV

Control

Logic

SPI

and

Frame-

Sync

Interface

IOVDD

DGNDAGND

DRDY/FSYNC

SCLK

DOUT[4:1]

DIN

ADS1174

MODE

Eight

Digital

Filters

VREFP VREFN

Input2

Input1

Input4

Input3

ADS1174

ADS1178

www.ti.com

........................................................................................................................................ SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008

Quad/Octal, Simultaneous Sampling, 16-Bit Analog-to-Digital Converters

234

• Simultaneously Sample Four/Eight Channels

The ADS1174 (quad) and ADS1178 (octal) are

multiple delta-sigma ( Δ Σ ) analog-to-digital converters

• Selectable Operating Modes:

(ADCs) with data rates up to 52k samples-per-second

High-Speed: 52kSPS Data Rate, 31mW/ch

(SPS), which allow synchronous sampling of four and

Low-Power: 10kSPS Data Rate, 7mW/ch

eight channels. These devices use identical

• AC Performance:

packages, and are also compatible with the

25kHz Bandwidth

high-performance 24-bit ADS1274 and ADS1278 ,

97dB SNR

permitting drop-in upgrades.

– 105dB THD

The delta-sigma architecture offers near ideal 16-bit

• DC Performance:

ac performance (97dB SNR, – 105dB THD, 1LSB

2 µ V/ ° C Offset Drift

linearity) combined with 0.005dB passband ripple and

2ppm/ ° C Gain Drift

linear phase response.

• Digital Filter:

The high-order, chopper-stabilized modulator

Linear Phase Response

achieves very low drift (2 µ V/ ° C offset, 2ppm/ ° C gain)

Passband Ripple: ± 0.005dB

and low noise (1LSB

). The on-chip finite impulse

Stop Band Attenuation: 100dB

response (FIR) filter provides a usable signal

bandwidth up to 90% of the Nyquist rate with 100dB

• Selectable SPI™ or Frame Sync Serial

of stop band attenuation while suppressing modulator

Interface

and signal out-of-band noise.

• Simple Pin-Driven Control

Two operating modes allow for optimization of speed

• Low Sampling Aperture Error

and power: High-speed mode (31mW/Ch at 52kSPS),

• Specified from – 40 ° C to +105 ° C

and Low-power mode (7mW/Ch at 10kSPS).

• Analog Supply: 5V

A SYNC input control pin allows the device

• I/O Supply: 1.8V to 3.3V

conversions to be started and synchronized to an

• Digital Core Supply: 1.8V

external event. SPI and Frame-Sync serial interfaces

are supported. The device is fully specified over the

extended industrial range ( – 40 ° C to +105 ° C) and is

available in an HTQFP-64 PowerPAD™ package.

• 3-Phase Power Monitors

• Defibrillators and ECG Monitors

• Coriolis Flow Meters

• Vibration/Modal Analysis

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 PowerPAD is a trademark of Texas Instruments.

3 SPI is a trademark of Motorola, Inc.

4 All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (39 pages)

PAGE 1
AD ADS1174 ADS1178 AD S1 174 S1 17 8 www.ti.com ........................................................................................................................................
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ADS1174 ADS1178 SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 ........................................................................................................................................ www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
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ADS1174 ADS1178 www.ti.com ........................................................................................................................................ SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 ELECTRICAL CHARACTERISTICS Limit specifications at TA = –40°C to +105°C. Typical specifications at TA = +25°C, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, and all channels active, unless otherwise noted.
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ADS1174 ADS1178 SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 ........................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS (continued) Limit specifications at TA = –40°C to +105°C. Typical specifications at TA = +25°C, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, and all channels active, unless otherwise noted.
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ADS1174 ADS1178 www.ti.com ........................................................................................................................................
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ADS1174 ADS1178 SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 ........................................................................................................................................ www.ti.com ADS1174/ADS1178 PIN DESCRIPTIONS (continued) PIN 6 NAME NO.
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ADS1174 ADS1178 www.ti.com ........................................................................................................................................ SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 TIMING CHARACTERISTICS: SPI FORMAT tCLK tCPW CLK · · · tCPW tCD tCONV DRDY tSD tDS tSCLK tSPW SCLK tSPW tMSBPD DOUT Bit 15 (MSB) tDOPD tDOHD Bit 14 tDIST Bit 13 tDIHD DIN TIMING REQUIREMENTS: SPI FORMAT For TA = –40°C to +105°C, IOVDD = 1.65V to 3.6V, and DVDD = 1.65V to 1.95V.
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ADS1174 ADS1178 SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 ........................................................................................................................................ www.ti.com TIMING CHARACTERISTICS: FRAME-SYNC FORMAT tCPW tCLK CLK tCPW tCS tFRAME tFPW tFPW FSYNC tFS tSCLK tSPW tSF SCLK tSPW tMSBPD DOUT tDOPD tDOHD Bit 15 (MSB) Bit 14 tDIST Bit 13 tDIHD DIN TIMING REQUIREMENTS: FRAME-SYNC FORMAT For TA = –40°C to +105°C, IOVDD = 1.65V to 3.
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ADS1174 ADS1178 www.ti.com ........................................................................................................................................ SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 OVERVIEW The ADS1174 (quad) and ADS1178 (octal) are 16-bit, delta-sigma ADCs. They offer the combination of excellent linearity, low noise, and low power consumption. Figure 1 shows the block diagram.
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ADS1174 ADS1178 SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 ........................................................................................................................................ www.ti.com FUNCTIONAL DESCRIPTION FREQUENCY RESPONSE The ADS1174 and ADS1178 are 16-bit delta/sigma ADCs consisting of independent converters that digitize input signals simultaneously. The ADS1174 consists of four independent converters, while the ADS1178 has eight independent converters.
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ADS1174 ADS1178 www.ti.com ........................................................................................................................................ SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 PHASE RESPONSE 0 The ADS1174/78 incorporates a multiple stage, linear phase digital filter.
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ADS1174 ADS1178 SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 ........................................................................................................................................ www.ti.com While the ADS1174/78 measures the differential input signal, the absolute input voltage is also important. This is the voltage on either input (AINP or AINN) with respect to AGND. The range for this voltage is: AVDD AGND –0.1V < (AINN or AINP) < AVDD + 0.
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ADS1174 ADS1178 www.ti.com ........................................................................................................................................ SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 VOLTAGE REFERENCE INPUTS (VREFP, VREFN) The voltage reference for the ADS1174/78 ADC is the differential voltage between VREFP and VREFN: VREF = (VREFP – VREFN). The voltage reference is common to all channels.
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ADS1174 ADS1178 SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 ........................................................................................................................................ www.ti.com MODE SELECTION (MODE) SYNCHRONIZATION (SYNC) The ADS1174/78 supports two modes of operation: High-Speed and Low-Power. These modes offer optimization of speed and power. The mode selection is determined by the status of the digital input MODE pins, as shown in Table 5.
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ADS1174 ADS1178 www.ti.com ........................................................................................................................................ SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 After synchronization, indication of valid data depends on the whether SPI or Frame-Sync format is used. In the SPI format, DRDY goes high as soon as SYNC is taken low; see Figure 13. After SYNC is returned high, DRDY stays high while the digital filter is settling.
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ADS1174 ADS1178 SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 ........................................................................................................................................ www.ti.com POWER-DOWN (PWDN) The ADS1174/78 measurement channels can be independently powered down by use of the PWDN inputs. To enter the power-down mode, hold the respective PWDN pin low for at least two fCLK cycles. To exit power-down, return the corresponding PWDN pin high.
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ADS1174 ADS1178 www.ti.com ........................................................................................................................................ SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 FORMAT[2:0] SERIAL INTERFACE PROTOCOLS Data can be read from the ADS1174/78 with two serial interface protocols (SPI or Frame-Sync) and several options of data formats (TDM/Discrete and Fixed/Dynamic data positions). The FORMAT[2:0] inputs are used to select among the options.
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ADS1174 ADS1178 SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 ........................................................................................................................................ www.ti.com DOUT In Discrete Data Output mode, the conversion data are output on the individual DOUT pins (DOUT1, DOUT2, etc.), whereas in TDM mode, data are output only on DOUT1. The MSB data are valid on DOUT[4:1]/[8:1] when DRDY goes low. The subsequent bits are shifted out with each falling edge of SCLK.
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ADS1174 ADS1178 www.ti.com ........................................................................................................................................ SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 DOUT MODES For both SPI and Frame-Sync interface protocols, either the data are shifted out through individual channel DOUT pins in a parallel data format (Discrete mode), or the data for all channels are shifted out in series through common pin DOUT1 (TDM mode).
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ADS1174 ADS1178 SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 ........................................................................................................................................ www.ti.com TDM Mode, Dynamic Position Data Discrete Data Output Mode In this TDM data output mode, when a channel is powered down, the data from higher channels shift one position in the data stream to fill the vacated data slot. Figure 19 shows the data stream with channel 1 and channel 3 powered down.
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ADS1174 ADS1178 www.ti.com ........................................................................................................................................ SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 DAISY-CHAINING The maximum number of channels that may be daisy-chained in this way is limited by the frequency of fSCLK, the mode selection, and the CLKDIV input. The frequency of fSCLK must be high enough to completely shift the data out from all channels within one fDATA period.
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ADS1174 ADS1178 SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 ........................................................................................................................................ www.ti.com To increase the number of data channels possible in a chain, a segmented DOUT scheme may be used, producing two data streams. Figure 23 illustrates four ADS1178s, with a pair of ADS1178s daisy-chained together.
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ADS1174 ADS1178 www.ti.com ........................................................................................................................................ SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 POWER SUPPLIES be sequenced at the same time if the supplies are tied together. Each supply has an internal reset circuit whose outputs are summed together to generate a global power-on reset.
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ADS1174 ADS1178 SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 ........................................................................................................................................ www.ti.com PIN TEST USING TEST[1:0] INPUTS Test mode allows continuity testing of the digital I/O pins. In this mode, the normal functions of the digital pins are disabled and routed to each other as pairs through internal logic, as shown in Table 13.
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ADS1174 ADS1178 www.ti.com ........................................................................................................................................ SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 APPLICATION INFORMATION To obtain the specified performance from the ADS1174/78, the following layout and component guidelines should be considered. 1. Power Supplies: The device requires three power supplies for operation: DVDD, IOVDD, and AVDD. The range for DVDD is 1.65V to 1.
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ADS1174 ADS1178 SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 ........................................................................................................................................ www.ti.com OPA1632 (1) +3.3V ADS1174 AINP1 (3) 10mF AINN1 AINP2 CLK AINN2 DRDY/FSYNC 50W IN2 2.2nF (3) IN3 2.2nF (3) AINN3 U1 AINP4 +5V 2.2nF + DVDD +1.
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ADS1174 ADS1178 www.ti.com ........................................................................................................................................ SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 1kW 1kW 2.7nF Buffered VCOM Output +15V (1) 49.9W VOCM VIN (2) AINP OPA1632 49.9W 0.1mF AINN -15V (1) 2.7nF 1kW (2) 1kW (1) Bypass with 10µF and 0.1µF capacitors. (2) 15nF for Low-Speed mode. Figure 27.
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ADS1174 ADS1178 SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 ........................................................................................................................................ www.ti.com PowerPAD THERMALLY-ENHANCED PACKAGING The PowerPAD concept is implemented in standard epoxy resin package material. The integrated circuit is attached to the leadframe die pad using thermally conductive epoxy.
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ADS1174 ADS1178 www.ti.com ........................................................................................................................................ SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 PowerPAD PCB Layout Considerations for the ADS1174/78 Figure 30 shows the recommended layer structure for thermal management when using a PowerPad package on a 4-layer PCB design. Note that the thermal pad is placed on both the top and bottom sides of the board.
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ADS1174 ADS1178 118mils (3mm) 40mils (1mm) 40mils (1mm) SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 ........................................................................................................................................ www.ti.com Package Outline Thermal Pad 40mils (1mm) 40mils (1mm) 118mils (3mm) 316mils (8mm) Thermal Via 13mils (0.33mm) 316mils (8mm) Figure 31.
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ADS1174 ADS1178 www.ti.com ........................................................................................................................................ SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 Revision History Changes from Revision A (December 2007) to Revision B ........................................................................................... Page • • • • • Corrected typo in the Absolute Maximum Ratings table...................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 21-May-2010 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS1174IPAPR HTQFP PAP 64 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 ADS1174IPAPT HTQFP PAP 64 250 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 ADS1178IPAPR HTQFP PAP 64 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1174IPAPR HTQFP PAP 64 1000 367.0 367.0 45.0 ADS1174IPAPT HTQFP PAP 64 250 367.0 367.0 45.0 ADS1178IPAPR HTQFP PAP 64 1000 367.0 367.0 45.0 ADS1178IPAPT HTQFP PAP 64 250 367.0 367.0 45.
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