ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Low-Power, 8-Channel, 16-Bit Analog Front-End for Biopotential Measurements Check for Samples: ADS1194, ADS1196, ADS1198 FEATURES 1 • 23 • • • • • • • • • • • • • • Eight Low-Noise PGAs and Eight High-Resolution ADCs (ADS1198) Low Power: 0.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS Minimum/maximum specifications apply from 0°C to +70°C. Typical specifications are at +25°C. All specifications at DVDD = 1.8V, AVDD – AVSS = 3V, VREF = 2.4V, external fCLK = 2.048MHz, data rate = 500SPS, and gain = 6, unless otherwise noted.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum/maximum specifications apply from 0°C to +70°C. Typical specifications are at +25°C. All specifications at DVDD = 1.8V, AVDD – AVSS = 3V, VREF = 2.4V, external fCLK = 2.048MHz, data rate = 500SPS, and gain = 6, unless otherwise noted.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum/maximum specifications apply from 0°C to +70°C. Typical specifications are at +25°C. All specifications at DVDD = 1.8V, AVDD – AVSS = 3V, VREF = 2.4V, external fCLK = 2.048MHz, data rate = 500SPS, and gain = 6, unless otherwise noted.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum/maximum specifications apply from 0°C to +70°C. Typical specifications are at +25°C. All specifications at DVDD = 1.8V, AVDD – AVSS = 3V, VREF = 2.4V, external fCLK = 2.048MHz, data rate = 500SPS, and gain = 6, unless otherwise noted.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com NOISE MEASUREMENTS The ADS1194/6/8 noise performance can be optimized by adjusting the data rate and PGA setting. As the averaging is increased by reducing the data rate, the noise drops correspondingly. Increasing the PGA value reduces the input-referred noise, which is particularly useful when measuring low-level biopotential signals.
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ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com BGA PIN ASSIGNMENTS (continued) (2) NAME TERMINAL FUNCTION DESCRIPTION RLDIN 3A Analog input Right leg drive input to MUX. If unused, short to AVDD.
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ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com TIMING CHARACTERISTICS tCLK CLK tCSSC tSCLK SCLK tCSH tSDECODE CS 1 tSPWL tSPWH 3 2 8 1 tDIHD tDIST tSCCS 3 2 8 tDOHD tDOPD DIN tCSDOZ tCSDOD Hi-Z Hi-Z DOUT NOTE: SPI settings are CPOL = 0 and CPHA = 1. Figure 1.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS All plots at TA = +25°C, AVDD = 3V, AVSS = 0V, DVDD = 1.8V, internal VREFP = 2.4V, VREFN = AVSS, external clock = 2.048MHz, data rate = 500SPS, and gain = 6, unless otherwise noted. INL vs TEMPERATURE INL vs PGA GAIN 1 1 +70°C +50°C +25°C 0°C 0.6 0.4 0.8 Integral Nonlinearity (LSB) Integral Nonlinearity (LSB) 0.8 0.2 0 -0.2 -0.4 -0.6 -0.8 0.6 0.4 0.2 0 -0.2 PGA 1 PGA 2 PGA 3 PGA 4 -0.4 -0.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) All plots at TA = +25°C, AVDD = 3V, AVSS = 0V, DVDD = 1.8V, internal VREFP = 2.4V, VREFN = AVSS, external clock = 2.048MHz, data rate = 500SPS, and gain = 6, unless otherwise noted.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com OVERVIEW The ADS1194/6/8 are low-power, multichannel, simultaneously-sampling, 16-bit delta-sigma (ΔΣ) analog-to-digital converters (ADCs) with integrated programmable gain amplifiers (PGAs). These devices integrate various ECG-specific functions that make them well-suited for scalable electrocardiogram (ECG), electroencephalography (EEG), and electromyography (EMG) applications.
Submit Documentation Feedback ADS1196 and ADS1198 Only Product Folder Link(s): ADS1194 ADS1196 ADS1198 EMI Filter EMI Filter EMI Filter EMI Filter EMI Filter EMI Filter EMI Filter EMI Filter AVSS AVSS1 MUX WCT From Wmuxb From Wmuxa B A RLD Amplifier PGA8 PGA7 PGA6 PGA5 PGA4 PGA3 PGA2 RLD RLD RLD IN REF OUT From Wmuxc C Power-Supply Signal PGA1 Temperature Sensor Input Test Signal Lead-Off Excitation Source RLD INV G = 0.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com EMI FILTER An RC filter at the input acts as an electromagnetic interference (EMI) filter on all of the channels. The –3dB filter bandwidth is approximately 3MHz. INPUT MULTIPLEXER The ADS1194/6/8 input multiplexers are very flexible and provide many configurable signal switching options. Figure 15 shows the multiplexer on a single channel of the device. Note that the device has eight such blocks, one for each channel.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Device Noise Measurements Setting CHnSET[2:0] = 001 sets the common-mode voltage of (AVDD – AVSS)/2 to both inputs of the channel. This setting can be used to test the inherent noise of the device in the user system. Test Signals (TestP and TestN) Setting CHnSET[2:0] = 101 provides internally-generated test signals for use in subsystem verification at power-up.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Supply Measurements (MVDDP, MVDDN) Setting CHnSET[2:0] = 011 sets the channel inputs to different supply voltages of the device. For channels 1, 2, 5, 6, 7, and 8, (MVDDP – MVDDN) is [0.5 × (AVDD – AVSS)]; for channel 3 and 4, (MVDDP – MVDDN) is DVDD/2. Note that to avoid saturating the PGA while measuring power supplies, the gain must be set to '1'.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com PGA SETTINGS AND INPUT RANGE The PGA is a differential input/differential output amplifier, as shown in Figure 19. It has seven gain settings (1, 2, 3, 4, 6, 8, and 12) that can be set by writing to the CHnSET register (see the CHnSET: Individual Channel Settings subsection of the Register Map section for details). The ADS1194/6/8 have CMOS inputs and hence have negligible current noise.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Input Differential Dynamic Range The differential (INP – INN) signal range depends on the analog supply and reference used in the system. This range is shown in Equation 3. VREF ±VREF Max (INP - INN) < ; Full-Scale Range = Gain Gain (3) The 3V supply, with a reference of 2.4V and a gain of 6 for ECGs, is optimized for power with a differential input signal of approximately 300mV.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com DIGITAL DECIMATION FILTER The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for higher data rates. Higher data rates are typically used in ECG applications for implement software pace detection and ac lead-off detection.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com The sinc filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these frequencies, the filter has infinite attenuation. Figure 21 shows the frequency response of the sinc filter and Figure 22 shows the roll-off of the sinc filter. With a step change at input, the filter takes 3 × tDR to settle. The fourth DRDY pulse is settled data.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com REFERENCE Figure 26 shows a simplified block diagram of the internal reference of the ADS1194/6/8. The reference voltage is generated with respect to AVSS. When using the internal voltage reference, connect VREFN to AVSS. 22mF VCAP1 R1 (1) Bandgap 2.4V or 4V R3 VREFP (1) 10mF R2 (1) VREFN AVSS To ADC Reference Inputs (1) For VREF = 2.4: R1 = 12.5kΩ, R2 = 25kΩ, and R3 = 25kΩ. For VREF = 4V: R1 = 10.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com CLOCK The ADS1194/6/8 provide two different methods for device clocking: internal and external. Internal clocking is ideally suited for low-power, battery-powered systems. The internal oscillator is trimmed for accuracy at room temperature. Over the specified temperature range the accuracy varies; see the Electrical Characteristics. Clock selection is controlled by the CLKSEL pin and the CLK_EN register bit.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com SPI INTERFACE The SPI-compatible serial interface consists of four signals: CS, SCLK, DIN, and DOUT. The interface reads conversion data, reads and writes registers, and controls the ADS1194/6/8 operation. The DRDY output is used as a status signal to indicate when data are ready. DRDY goes low when new data are available. Chip Select (CS) Chip select (CS) selects the ADS1194/6/8 for SPI communication.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Data Output (DOUT) The data output pin (DOUT) is used with SCLK to read conversion and register data from the ADS1194/6/8. Data on DOUT are shifted out on the rising edge of SCLK. DOUT goes to a high-impedance state when CS is high. In read data continuous mode (see the SPI Command Definitions section for more details), the DOUT output line also indicates when new data are available.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Data Ready (DRDY) DRDY is an output. When it transitions low, new conversion data are ready. The CS signal has no effect on the data ready signal. The behavior of DRDY is determined by whetehr the device is in RDATAC mode or the RDATA command is being used to read data on demand. (See the RDATAC: Read Data Continuous and RDATA: Read Data subsections of the SPI Command Definitions section for further detials).
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Reset (RESET) There are two methods to reset the ADS1194/6/8: pull the RESET pin low, or send the RESET opcode command. When using the RESET pin, take it low to force a reset. Make sure to follow the minimum pulse width timing specifications before taking the RESET pin back high. The RESET command takes effect on the eighth SCLK falling edge of the opcode command.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Continuous Mode Conversions begin when the START pin is taken high for at least two tCLKs or when the START opcode command is sent. As seen in Figure 32, the DRDY output goes high when conversions are started and goes low when data are ready. Conversions continue indefinitely until the START pin is taken low or the STOP opcode command is transmitted.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Single-Shot Mode The single-shot mode is enabled by setting the SINGLE_SHOT bit in CONFIG4 register to '1'. In single-shot mode, the ADS1194/6/8 perform a single conversion when the START pin is taken high for at least two tCLKs, or when the START opcode command is sent. As seen in Figure 34, when a conversion is complete, DRDY goes low and further conversions are stopped.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com When using multiple devices, the devices can be synchronized with the START signal. The delay from START to the DRDY signal is fixed for a fixed data rate (see the START subsection of the SPI Interface section for more details on the settling times). Figure 35 shows the behavior of two devices when synchronized with the START signal.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Standard Mode Figure 36a shows a configuration with two devices cascaded together. One of the devices is an ADS1198 (eight-channel) and the other is an ADS1194 (four-channel). Together, they create a system with 12 channels. DOUT, SCLK, and DIN are shared. Each device has its own chip select. When a device is not selected by the corresponding CS being driven to logic 1, the DOUT of this device is high-impedance.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Note that from Figure 2, the SCLK rising edge shifts data out of the ADS1194/6/8 on DOUT. The SCLK rising edge is also used to latch data into the device DAISY_IN pin down the chain. This architecture allows for a faster SCLK rate speed, but it also makes the interface sensitive to board level signal delays. The more devices in the chain, the more challenging it could become to adhere to setup and hold times.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com SPI COMMAND DEFINITIONS The ADS1194/6/8 provide flexible configuration control. The opcode commands, summarized in Table 9, control and configure the operation of the ADS1194/6/8. The opcode commands are stand-alone, except for the register read and register write operations that require a second command byte plus data.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com STOP: Stop Conversions This opcode stops conversions. Tie the START pin low to control conversions by command. When the STOP command is sent, the conversion in progress completes and further conversions are stopped. If conversions are already stopped, this command has no effect. There are no restrictions on the SCLK rate for this command and it can be issued any time.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com RDATA: Read Data Issue this command after DRDY goes low to read the conversion result (in Stop Read Data Continuous mode). There is no restriction on the SCLK rate for this command, and there is no wait time needed for the subsequent commands or data retrieval SCLKs. To retrieve data from the device after RDATA command is issued, make sure either the START pin is high or the START command is issued.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com RREG: Read From Register This opcode reads register data. The Register Read command is a two-byte opcode followed by the output of the register data. The first byte contains the command opcode and the register address. The second byte of the opcode specifies the number of registers to read – 1. First opcode byte: 0010 rrrr, where rrrr is the starting register address.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com REGISTER MAP Table 10 describes the various ADS1194/6/8 registers. Table 10.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com User Register Description ID: ID Control Register (Factory-Programmed, Read-Only) Address = 00h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DEV_ID5 DEV_ID4 DEV_ID3 1 0 DEV_ID2 DEV_ID1 DEV_ID0 The ID Control Register is programmed during device manufacture to indicate device characteristics. Bits[7:5] DEV_ID[5:3]: Device family identification These bits indicate the device family.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com CONFIG1: Configuration Register 1 Address = 01h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 DAISY_EN CLK_EN 0 0 DR2 DR1 DR0 Bit 7 Must always be set to '0' Bit 6 DAISY_EN: Daisy-chain/multiple readback mode This bit determines which mode is enabled.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com CONFIG2: Configuration Register 2 Address = 02h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 1 INT_TEST 0 TEST_AMP TEST_FREQ1 TEST_FREQ0 Configuration Register 2 configures the test signal generation. See the Input Multiplexer section for more details.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com CONFIG3: Configuration Register 3 Address = 03h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PD_REFBUF 1 VREF_4V RLD_MEAS RLDREF_INT PD_RLD RLD_LOFF_SENS RLD_STAT Configuration Register 3 configures multi-reference and RLD operation. Bit 7 PD_REFBUF: Power-down reference buffer This bit determines the power-down reference buffer state.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com LOFF: Lead-Off Control Register Address = 04h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 COMP_TH2 COMP_TH1 COMP_TH0 VLEAD_OFF_EN ILEAD_OFF1 ILEAD_OFF0 FLEAD_OFF1 FLEAD_OFF0 The Lead-Off Control Register configures the Lead-Off detection operation. Bits[7:5] COMP_TH[2:0]: Lead-off comparator threshold These bits determine the lead-off comparator threshold level setting.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com CHnSET: Individual Channel Settings (n = 1:8) Address = 05h to 0Ch BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PD GAIN2 GAIN1 GAIN0 0 MUXn2 MUXn1 MUXn0 The CH[1:8]SET Control Register configures the power mode, PGA gain, and multiplexer settings channels. See the Input Multiplexer section for details. CH[2:8]SET are similar to CH1SET, corresponding to the respective channels.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com LOFF_SENSP Address = 0Fh BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 LOFF8P LOFF7P LOFF6P LOFF5P LOFF4P LOFF3P LOFF2P LOFF1P This register selects the positive side from each channel for lead-off detection. See the Lead-Off Detection subsection of the ECG-Specific Functions section for details. Note that the LOFF_STATP register bits are only valid if the corresponding LOFF_SENSP bits are set to '1'.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com GPIO: General-Purpose I/O Register Address = 14h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 GPIOD4 GPIOD3 GPIOD2 GPIOD1 GPIOC4 GPIOC3 GPIOC2 GPIOC1 The General-Purpose I/O Register controls the action of the three GPIO pins. Bits [7:4] GPIOD[4:1]: GPIO data These bits are used to read and write data to the GPIO ports.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com RESERVED Address = 16h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 0 0 0 0 0 0 Bits [7:0] Must always be set to '0' CONFIG4: Configuration Register 4 Address = 17h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 0 0 SINGLE_SHOT WCT_TO_RLD PD_LOFF_COMP 0 Bits [7:4] Must always be set to '0' Bit [3] SINGLE_SHOT: Single-shot conversion This bit sets the conversion mode.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com WCT1: Wilson Center Terminal and Augmented Lead Control Register Address = 18h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 aVF_CH6 aVL_CH5 aVR_CH7 aVR_CH4 PD_WCTA WCTA2 WCTA1 WCTA0 The WCT1 control register configures the device WCT circuit channel selection and the augmented leads.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com WCT2: Wilson Center Terminal Control Register Address = 19h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PD_WCTC PD_WCTB WCTB2 WCTB1 WCTB0 WCTC2 WCTC1 WCTC0 The WCT2 configuration register configures the device WCT circuit channel selection.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com ECG-SPECIFIC FUNCTIONS INPUT MULTIPLEXER (REROUTING THE RIGHT LEG DRIVE SIGNAL) The input multiplexer has ECG-specific functions for the right-leg drive signal. The RLD signal is available at the RLDOUT pin once the appropriate channels are selected for the RLD derivation, feedback elements are installed external to the chip, and the loop is closed.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com INPUT MULTIPLEXER (MEASURING THE RIGHT LEG DRIVE SIGNAL) Also, the RLDOUT signal can be routed to a channel (that is not used for the calculation of RLD) for measurement. Figure 43 shows the register settings to route the RLDIN signal to channel 8. The measurement is done with respect to the voltage on the RLDREF pin. If RLDREF is chosen to be internal, it would be at (AVDD + AVSS)/2.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com WILSON CENTER TERMINAL (WCT) AND CHEST LEADS In the standard 12-lead ECG, WCT voltage is defined as the average of Right Arm (RA), Left Arm (LA), and Left Leg (LL) electrodes. This voltage is used as the reference voltage for the measurement of the chest leads. The ADS1194/6/8 has three integrated low-noise amplifiers that generate the WCT voltage. Figure 44 shows the block diagram of the implementation.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com As mentioned previously in this section, all three WCT amplifiers can be connected to one of the eight analog input pins. The inputs of the amplifiers are chopped and the chopping frequency is at 8kHz. The chop frequency shows itself at the output of the WCT amplifiers as a small square-wave riding on dc. The amplitude of the square-wave is the offset of the amplifier and is typically 5mVPP.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com LEAD-OFF DETECTION Patient electrode impedances are known to decay over time. It is necessary to continuously monitor these electrode connections to verify a suitable connection is present. The ADS1194/6/8 lead-off detection functional block provides significant flexibility to the user to choose from various lead-off detection strategies. Though called lead-off detection, this is in fact an electrode-off detection.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com DC Lead-Off In this method, the lead-off excitation is with a dc signal. The dc excitation signal can be chosen from either a pull-up/pull-down resistor or a current source/sink, shown in Figure 47. The selection is done by setting the VLEAD_OFF_EN bit in the LOFF register. One side of the channel is pulled to supply and the other side is pulled to ground.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com AC Lead-Off In this method, an out-of-band ac signal is used for excitation. The ac signal is generated by alternatively providing pull-up resistors and pull-down resistors at the input with a fixed frequency. The ac signal is passed through an anti-aliasing filter to avoid aliasing. The frequency can be chosen by the FLEAD_OFF[1:0] bits in the LOFF register.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com RIGHT LEG DRIVE (RLD DC BIAS CIRCUIT) The right leg drive (RLD) circuitry is used as a means to counter the common-mode interference in a ECG system as a result of power lines and other sources, including fluorescent lights. The RLD circuit senses the common-mode of a selected set of electrodes and creates a negative feedback loop by driving the body with an inverted common-mode signal.
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ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com WCT as RLD In certain applications, the right leg drive is derived as the average of RA, LA, and LL. This level is the same as the WCT voltage. The WCT amplifier has limited drive strength and thus should be used only to drive very high impedances directly. As shown in Figure 51, the ADS1194/6/8 provide an option to internally buffer the WCT signal by setting the WCT_TO_RLD bit in the CONFIG4 register.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com PACE DETECT The ADS1194/6/8 provide flexibility for pace detection with external hardware by bringing out the output of the PGA at two pins: TESTP_PACE_OUT1 and TESTN_PACE_OUT2. External Hardware Approach The ADS1194/6/8 provide the option of bringing out the output of the PGA; see Figure 53. External hardware circuitry can be used to detect the presence of the pulse.
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ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com QUICK-START GUIDE PCB LAYOUT Power Supplies and Grounding The ADS1194/6/8 have three supplies: AVDD, AVDD1, and DVDD. Both AVDD and AVDD1 should be as quiet as possible. AVDD1 provides the supply to the charge pump block and has transients at fCLK. Therefore, it is recommended that AVDD1 and AVSS1 be star-connected to AVDD and AVSS.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Connecting the Device to Bipolar (±1.5V/1.8V) Supplies Figure 55 illustrates the ADS1194/6/8 connected to a bipolar supply. In this example, the analog supplies connect to the device analog supply (AVDD). This supply is referenced to the device analog return (AVSS), and the digital supplies (DVDD and DVDD) are referenced to the device digital ground return (DVDD). +1.5V +1.8V 1mF 0.1mF 0.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com POWER-UP SEQUENCING Before device power-up, all digital and analog inputs must be low. At the time of power-up, all of these signals should remain low until the power supplies have stabilized, as shown in Figure 57. At this time, begin supplying the master clock signal to the CLK pin. Wait for time tPOR, then transmit a RESET pulse.
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Analog/Digital Power-Up Set CLKSEL Pin = 0 and Provide External Clock fCLK = 2.
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ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (April 2011) to Revision C Page • Added eighth Features bullet ................................................................................................................................................ 1 • Changed first paragraph of Description section ............................
ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com Changes from Revision A (September 2010) to Revision B Page • Updated Family and Ordering Information table ................................................................................................................... 2 • Added Digital Filter section to Electrical Characteristics table ..............................................................................................
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PACKAGE OPTION ADDENDUM www.ti.com 29-Nov-2011 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS1194CPAGR TQFP PAG 64 1500 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 ADS1194CZXGR NFBGA ZXG 64 1000 330.0 16.4 8.3 8.3 2.25 12.0 16.0 Q1 ADS1194CZXGT NFBGA ZXG 64 250 330.0 16.4 8.3 8.3 2.25 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1194CPAGR TQFP PAG 64 1500 367.0 367.0 45.0 ADS1194CZXGR NFBGA ZXG 64 1000 336.6 336.6 28.6 ADS1194CZXGT NFBGA ZXG 64 250 336.6 336.6 28.6 ADS1196CPAGR TQFP PAG 64 1500 367.0 367.0 45.0 ADS1196CZXGR NFBGA ZXG 64 1000 336.6 336.6 28.6 ADS1196CZXGT NFBGA ZXG 64 250 336.6 336.6 28.
MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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