Datasheet

ADS1209

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SBAS491 –FEBRUARY 2010

LAYOUT CONSIDERATIONS

POWER SUPPLIES DECOUPLING

An applied external digital filter rejects high-frequency Good decoupling practices must be used for the

noise. PSRR and CMRR improve at higher ADS1209 and for all components in the design. All

frequencies because the digital filter suppresses decoupling capacitors, specifically the 0.1mF ceramic

high-frequency noise. However, the suppression of capacitors, must be placed as close as possible to

the filter is not infinite while high-frequency noise the pin being decoupled. A 1mF and 10mF capacitor,

continues to influence the conversion result. in parallel with the 0.1mF ceramic capacitor, can be

used to decouple AVDD to AGND as well as BVDD

Inputs to the ADS1209, such as CHx+, CHx–, and

to BGND. At least one 0.1mF ceramic capacitor must

CLKIN, should not be present before the power

be used to decouple every AVDD to AGND and

supply is on. Violating this condition could cause

BVDD to BGND, as well as for the digital supply on

latch-up. If these signals are present before the

each digital component.

supply is on, series resistors should be used to limit

the input current to a maximum of 10mA. The digital supply sets the I/O voltage for the

interface and can be set within a range of 2.7V to

5.5V.

GROUNDING

In cases where both the analog and digital I/O

Analog and digital sections of the design must be

supplies share the same supply source, an RC filter

carefully and cleanly partitioned. Each section should

of 10Ω and 0.1mF can be used to help reduce the

have its own ground plane with a connection between

noise in the analog supply.

them underneath the converter.

For multiple converters, connect the two ground

planes as close as possible to each of the converters.

Product Folder Link(s): ADS1209