Datasheet

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ADS1210

ADS1211

24-Bit ANALOG-TO-DIGITAL CONVERTER

FEATURES

● DELTA-SIGMA A/D CONVERTER

● 23 BITS EFFECTIVE RESOLUTION AT 10Hz

AND 20 BITS AT 1000Hz

● DIFFERENTIAL INPUTS

● PROGRAMMABLE GAIN AMPLIFIER

● FLEXIBLE SPI

™

-COMPATIBLE SSI

INTERFACE WITH 2-WIRE MODE

● PROGRAMMABLE CUT-OFF FREQUENCY

UP TO 15.6kHz

● INTERNAL/EXTERNAL REFERENCE

● ON-CHIP SELF-CALIBRATION

● ADS1211 INCLUDES 4-CHANNEL MUX

DESCRIPTION

The ADS1210 and ADS1211 are precision, wide dynamic

range, delta-sigma Analog-to-Digital (A/D) converters with

24-bit resolution operating from a single +5V supply. The

differential inputs are ideal for direct connection to transduc-

ers or low-level voltage signals. The delta-sigma architec-

ture is used for wide dynamic range and to ensure 22 bits

of no-missing-code performance. An effective resolution of

23 bits is achieved through the use of a very low-noise input

amplifier at conversion rates up to 10Hz. Effective resolu-

tions of 20 bits can be maintained up to a sample rate of

1kHz through the use of the unique Turbo modulator mode

of operation. The dynamic range of the converters is further

increased by providing a low-noise programmable gain

amplifier with a gain range of 1 to 16 in binary steps.

The ADS1210 and ADS1211 are designed for high resolution

measurement applications in smart transmitters, industrial

process control, weigh scales, chromatography, and portable

instrumentation. Both converters include a flexible synchro-

nous serial interface that is SPI-compatible and also offers a

two-wire control mode for low cost isolation.

The ADS1210 is a single-channel converter and is offered in

both 18-pin DIP and 18-lead SOIC packages. The ADS1211

includes a 4-channel input multiplexer and is available in 24-

pin DIP, 24-lead SOIC, and 28-lead SSOP packages.

APPLICATIONS

● INDUSTRIAL PROCESS CONTROL

● INSTRUMENTATION

● BLOOD ANALYSIS

● SMART TRANSMITTERS

● PORTABLE INSTRUMENTS

● WEIGH SCALES

● PRESSURE TRANSDUCERS

ADS1211

PGA

+2.5V

Reference

+3.3V Bias

Generator

Clock Generator

Serial Interface

Second-Order

∆∑

Modulator

Instruction Register

Command Register

Data Output Register

Offset Register

Full-Scale Register

Third-Order

Digital Filter

Micro Controller

Modulator Control

AGND AV

REF

OUT

REF

BIAS

OUT

MODE

DSYNCADS1211 Only ADS1210/11 CS DRDY

SCLK

DGND

SDIO

SDOUT

MUX

SBAS034B – JANUARY 1996 – REVISED SEPTEMBER 2005

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

Summary of content (50 pages)

PAGE 1
ADS1 ADS1210 ADS1211 210 ADS 1211 ADS1 ADS1 211 ADS1 210 211 SBAS034B – JANUARY 1996 – REVISED SEPTEMBER 2005 24-Bit ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● DELTA-SIGMA A/D CONVERTER ● 23 BITS EFFECTIVE RESOLUTION AT 10Hz AND 20 BITS AT 1000Hz ● DIFFERENTIAL INPUTS ● PROGRAMMABLE GAIN AMPLIFIER ● FLEXIBLE SPI™-COMPATIBLE SSI INTERFACE WITH 2-WIRE MODE ● PROGRAMMABLE CUT-OFF FREQUENCY UP TO 15.
PAGE 2
SPECIFICATIONS All specifications TMIN to TMAX, AVDD = DVDD = +5V, fXIN = 10MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REFOUT disabled,VBIAS disabled, and external 2.5V reference, unless otherwise specified.
PAGE 3
SPECIFICATIONS (CONT) All specifications TMIN to TMAX, AVDD = DVDD = +5V, fXIN = 10MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REFOUT disabled,VBIAS disabled, and external 2.5V reference, unless otherwise specified. ADS1210U, P/ADS1211U, P, E PARAMETER CONDITIONS POWER SUPPLY REQUIREMENTS Power Supply Voltage Power Supply Current: Analog Current Digital Current Additional Analog Current with REFOUT Enabled VBIAS Enabled Power Dissipation MIN TYP 4.
PAGE 4
ADS1210 SIMPLIFIED BLOCK DIAGRAM AGND AVDD 3 16 REF OUT REF IN VBIAS 17 18 4 +2.5V Reference AINP AINN XOUT 7 +3.
PAGE 5
ADS1211 SIMPLIFIED BLOCK DIAGRAM AIN1P AIN1N AIN2P AIN2N AIN3P AIN3N AIN4P AIN4N AGND AVDD 6 19 REFOUT REFIN VBIAS 20 21 7 +2.5V Reference 4 XIN XOUT 10 +3.
PAGE 6
ADS1211E PIN CONFIGURATION TOP VIEW SSOP AIN3N 1 28 AIN3P AIN2P 2 27 AIN4N AIN2N 3 26 AIN4P AIN1P 4 25 REFIN AIN1N 5 24 REFOUT AGND 6 23 AVDD VBIAS 7 NIC 8 NIC 9 CS 10 DSYNC 11 6 ADS1211E PIN DEFINITIONS PIN NO NAME DESCRIPTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 AIN3N AIN2P AIN2N AIN1P AIN1N AGND VBIAS NIC NIC CS DSYNC XIN XOUT DGND DVDD SCLK SDIO 18 19 20 21 22 23 24 25 26 27 28 SDOUT DRDY NIC NIC MODE AVDD REFOUT REFIN AIN4P AIN4N AIN3P Inverting Input Channel 3.
PAGE 7
TYPICAL PERFORMANCE CURVES At TA = +25°C, AVDD = DVDD = +5V, fXIN = 10MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of one, REFOUT disabled, VBIAS disabled, and external 2.5V reference, unless otherwise noted. EFFECTIVE RESOLUTION vs DATA RATE (1MHz Clock) EFFECTIVE RESOLUTION vs DATA RATE (2.
PAGE 8
TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, AVDD = DVDD = +5V, fXIN = 10MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REFOUT disabled, VBIAS disabled, and external 2.5V reference, unless otherwise noted. POWER DISSIPATION vs TURBO MODE RATE (REFOUT Enabled) POWER DISSIPATION vs TURBO MODE RATE (External Reference; REFOUT) 40.0 Power Dissipation (mW) Power Dissipation (mW) 50.0 40.0 10MHz 5MHz 30.0 2.5MHz 30.0 10MHz 5MHz 20.0 2.5MHz 1MHz 1MHz 20.0 10.
PAGE 9
THEORY OF OPERATION The ADS1210 and ADS1211 are precision, high dynamic range, self-calibrating, 24-bit, delta-sigma A/D converters capable of achieving very high resolution digital results. Each contains a programmable gain amplifier (PGA); a second-order delta-sigma modulator; a programmable digital filter; a microcontroller including the Instruction, Command and Calibration registers; a serial interface; a clock generator circuit; and an internal 2.5V reference.
PAGE 10
DATA RATE (HZ) -3DB FREQUENCY (HZ) G=1 G=2 G=4 G=8 G = 16 10 25 30 50 60 100 250 500 1000 2.62 6.55 7.86 13.1 15.7 26.2 65.5 131 262 21.5 20.5 20.5 20.0 19.5 18.0 15.0 12.5 10.0 21.0 20.5 20.5 20.0 19.5 18.0 15.0 12.5 10.5 21.0 20.5 20.5 20.0 19.5 18.0 15.0 12.5 10.0 21.0 20.0 20.0 19.5 19.0 18.0 15.0 12.5 10.0 20.0 19.5 19.5 19.0 19.0 18.0 15.0 12.5 10.0 EFFECTIVE RESOLUTION (BITS RMS) TABLE III. Effective Resolution vs Data Rate and Gain Setting. (Turbo Mode Rate of 1 and a 10MHz clock.
PAGE 11
fXIN—The frequency of the crystal oscillator or CMOS compatible input signal at the XIN input of the ADS1210/11. NORMALIZED DIGITAL FILTER RESPONSE 0 fMOD—The frequency or speed at which the modulator of the ADS1210/11 is running, given by the following equation: f XIN • Turbo Mode 512 fSAMP—The frequency or switching speed of the input sampling capacitor.
PAGE 12
Filter Equation The digital filter is described by the following transfer function:  π • f • N sin    f MOD  | H (f ) | =  π•f  N • sin    f MOD  3 In a Turbo Mode Rate of 16, the ADS1210/11 can offer 20 bits of effective resolution at a 1kHz data rate. A comparison of effective resolution versus Turbo Mode Rates and output data rates is shown in Table IV while Table V shows the corresponding noise level in µVrms. where N is the Decimation Ratio.
PAGE 13
The Turbo Mode Rate (TMR) is programmed via the Sampling Frequency bits of the Command Register. Due to the increase in input capacitor sampling frequency, higher Turbo Mode settings result in lower analog input impedance; AIN Impedance (Ω) = (10MHz/fXIN)•4.3E6/(G•TMR) where G is the gain setting.
PAGE 14
Normal Mode Valid Data Normal Mode Self-Calibration Mode Offset Calibration on Internal Offset(2) Valid Data Full-Scale Calibration on Internal Full-Scale Analog Input Conversion Valid Data Valid Data DRDY SC(1) Serial I/O tDATA NOTES: (1) SC = Self-Calibration instruction. (2) In Slave Mode, this function requires 4 cycles. FIGURE 5. Self-Calibration Timing.
PAGE 15
Normal operation returns within a single conversion cycle because it is assumed that the input voltage at the converter’s input is not removed immediately after the full-scale calibration is performed. In this case, the digital filter already contains a valid result. input. Conversions proceed as usual over the next three cycles in order to fill the digital filter. DRDY remains HIGH during this time. On the next cycle, the DRDY signal goes LOW indicating valid data and resumption of normal operation.
PAGE 16
Also, during this cycle, the sampling capacitor is disconnected from the converter’s analog input and is connected across REFIN. A gain calibration is initiated and proceeds over the next three conversions. After this, the input capacitor is once again connected to the analog input. Conversions proceed as usual over the next three cycles in order to fill the digital filter. DRDY remains HIGH during this time.
PAGE 17
considerations associated with VBIAS and the settling of external circuitry. All of these must be taken into account when determining the amount of time required to resume normal operation. The timing diagram shown in Figure 10 does not take into account the settling of external circuitry.
PAGE 18
R1 3kΩ ±10V AINP REFIN ±10V AINN REFOUT R2 3kΩ R4 1kΩ R3 1kΩ AGND AVDD VBIAS AGND MODE DGND GND DSYNC XTAL DGND AVDD ADS1210 DRDY CS DVDD C1 12pF 1.0µF C2 12pF SDOUT XIN SDIO XOUT SCLK DGND DVDD DVDD DGND FIGURE 12. ±10V Input Configuration Using VBIAS. The circuitry which generates the +2.5V reference can be disabled via the Command Register and will result in a lower power dissipation. The reference circuitry consumes a little over 1.6mA of current with no external load.
PAGE 19
The Command Register (CMR) controls all of the ADS1210/ 11’s options and operating modes. These include the PGA gain setting, the Turbo Mode Rate, the output data rate (decimation ratio), etc. The CMR is the only 32-bit register within the ADS1210/11. It, and all the remaining registers, may be read from or written to. Instruction Register (INSR) The INSR is an 8-bit register which commands the serial interface either to read or to write “n” bytes beginning at the specified register location.
PAGE 20
DF (Data Format) Bit—The DF bit controls the format of the output data, either Two’s Complement or Offset Binary, as follows: DF FORMAT ANALOG INPUT SDL (Serial Data Line) Bit—The SDL bit controls which pin on the ADS1210/11 will be used as the serial data output pin, either SDIO or SDOUT, as follows: DIGITAL OUTPUT SDL SERIAL DATA OUTPUT PIN 0 1 SDIO SDOUT 0 Two’s Complement +Full-Scale Zero –Full-Scale 7FFFFFH 000000H 800000H 1 Offset Binary +Full-Scale Zero –Full-scale FFFFFFH 800000H 000
PAGE 21
DATA RATE (HZ) DECIMATION RATIO DR12 DR11 DR10 DR9 DR8 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 1000 500 250 100 60 50 20 10 19 38 77 194 325 390 976 1952 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 0 0 1 1 1 0 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 0 0 1 0 1 0 1 0 0 0 Table XI. Decimation Ratios vs Data Rates (Turbo Mode rate of 1 and 10MHz clock).
PAGE 22
Offset Calibration Register (OCR) The OCR is a 24-bit register which contains the offset correction factor that is applied to the conversion result before it is placed in the Data Output Register (see Table XIII). In most applications, the contents of this register will be the result of either a self-calibration or a system calibration. The OCR is both readable and writeable via the serial interface.
PAGE 23
SYMBOL DESCRIPTION MIN MAX UNITS fXIN XIN Clock Frequency 0.5 10 MHz tXIN XIN Clock Period 100 2000 XIN Clock High 0.4 • tXIN t3 XIN Clock LOW 0.
PAGE 24
t16 DRDY t18 t17 SCLK SDIO IN7 IN1 IN0 INM IN1 IN0 OUT1 OUT0 OUT1 OUT0 Write Register Data IN7 SDIO IN1 IN0 OUTM Read Register Data using SDIO IN7 SDIO IN1 IN0 SDOUT OUTM Read Register Data using SDOUT FIGURE 16. Serial Interface Timing (CS LOW), Master Mode.
PAGE 25
DRDY t20 t21 t37 CS t24 t19 t23 SCLK IN7 SDIO IN1 IN0 t24 INM IN1 IN0 IN7 OUTM OUT1 OUT0 IN7 Write Register Data IN7 SDIO IN1 IN0 Read Register Data Using SDIO IN7 SDIO IN1 IN0 IN7 OUTM SDOUT OUT1 OUT0 Read Register Data Using SDOUT DRDY t16 t20 CS SCLK OUTM SDIO OUT1 OUT0 Continuous Read of Data Output Register using SDIO OUTM SDOUT OUT1 OUT0 Continuous Read of Data Output Register using SDOUT FIGURE 19. Serial Interface Timing (Using CS), Slave Mode.
PAGE 26
Synchronizing Multiple Converters A negative going pulse on DSYNC can be used to synchronize multiple ADS1210/11s. This assumes that each ADS1210/11 is driven from the same master clock and is set to the same Decimation Ratio and Turbo Mode Rate. The effect that this signal has on data output timing in general is discussed in the Serial Interface section. The concern here is what happens if the DSYNC input is completely asynchronous to this master clock.
PAGE 27
For example, Figure 24 shows that just prior to the DRDY signal going LOW, the internal Data Output Register (DOR) is updated. This update involves the Offset Calibration Register (OCR) and the Full-Scale Register (FSR). If the OCR or FSR are being written, their final value may not be correct, and the result placed into the DOR will certainly not be valid. Problems can also arise if certain bits of the Command Register are being changed. Note that reading the Data Output Register is an exception.
PAGE 28
Start Reading From Read Flowchart Start Writing ADS1210/11 drives DRDY LOW To Write Flowchart ADS1210/11 drives DRDY LOW CS taken HIGH for 10.5 t XIN periods minimum (see text if CS tied LOW). CS state HIGH LOW CS state CS state HIGH HIGH Continuous Read Mode? LOW LOW CS taken HIGH for 10.5 tXIN periods minimum (see text if CS tied LOW).
PAGE 29
Using CS and Continuous Read Mode The serial interface may make use of the CS signal, or this input may simply be tied LOW. There are several issues associated with choosing to do one or the other. The CS signal does not directly control the tri-state condition of the SDOUT or SDIO output. These signals are normally in the tri-state condition. They only become active when serial data is being transmitted from the ADS1210/11.
PAGE 30
If a serial communication does not occur during any conversion period, the ADS1210/11 will continue to operate properly. However, the results in the Data Output Register will be lost when they are overwritten by the new result at the start of the next conversion period. Just prior to this update, DRDY will be forced HIGH and will return LOW after the update. nication to and from the ADS1210/11 should not occur for at least 25ms after power is stable.
PAGE 31
Three-Wire Interface Figure 28 shows a three-wire interface with a 8xC32 microprocessor. Note that the Slave Mode is being selected and the SDIO pin is being used for input and output. Figure 29 shows a different type of three-wire interface with a 8xC51 microprocessor. Here, the Master Mode is used. The interface signals consist of SDOUT, SDIO, and SCLK. P1.0 8xC32 P1.1 P1.2 AVDD P1.3 P1.4 AINP REFIN AINN REFOUT AGND AGND DVDD CS P1.6 AVDD VBIAS P1.5 1.0µF AGND P1.
PAGE 32
Four-Wire Interface Figure 30 shows a four-wire interface with a 8xC32 microprocessor. Again, the Slave Mode is being used. Note that the XIN input can also be controlled. It is possible with some microcontrollers and digital signal processors to produce a continuous serial clock, which could be connected to the XIN input. The frequency of the clock is often settable over some range.
PAGE 33
PB7 XIRQ PB6 RESET PB5 PC7 PB4 PC6 AINP REFIN PC5 AINN REFOUT PB3 68HC11 AVDD PC4 AGND PB1 PC3 VBIAS PB0 PC2 PE0 PC1 PE1 PC0 PB2 PE2 AGND CS XTAL XTAL DGND AVDD AGND MODE R1 10kΩ ADS1210 DRDY DSYNC C1 12pF 1.0µF SDOUT XIN SDIO XOUT SCLK DGND DVDD R2 10kΩ DVDD C2 12pF FIGURE 32. Full Interface with a 68HC11 Microprocessor.
PAGE 34
SOURCE CURRENT 30 AIN3N AIN3P AIN2P AIN4N AIN2N AIN4P +5V 25 20 IOUT (mA) –40°C 25°C +5V 85°C 15 +5V 10 C1 12pF XTAL DGND 0 1 2 3 4 REFIN AIN1N REFOUT AGND AVDD ADS1211U, P VBIAS MODE CS DRDY C2 12pF XIN SDIO XOUT SCLK DGND DVDD REF1004 +2.5V 1.0µF AVDD +5V SDOUT DSYNC 5 0 AIN1P R1 49.9kΩ +5V VOH VOH 0V P1 2kΩ +5V 5 DGND VOH (V) FIGURE 34. Source Current vs VOH for SDOUT Under Worst-Case Conditions.
PAGE 35
LAYOUT POWER SUPPLIES The ADS1210/11 requires the digital supply (DVDD) to be no greater than the analog supply (AVDD) +0.3V. In the majority of systems, this means that the analog supply must come up first, followed by the digital supply. Failure to observe this condition could cause permanent damage to the ADS1210/11. Inputs to the ADS1210/11, such as SDIO, AIN, or REFIN, should not be present before the analog and digital supplies are on. Violating this condition could cause latch-up.
PAGE 36
APPLICATIONS The ADS1210/11 can be used in a broad range of data acquisition tasks. The following application diagrams show the ADS1210 and/or ADS1211 being used for bridge transducer measurements, temperature measurement, and 4-20mA receiver applications. 1/2 OPA1013 AVDD AGND 3kΩ AINP REFIN AINN REFOUT AGND AGND AGND DVDD MODE C2 12pF AGND ADS1210 DRDY DSYNC XTAL DGND VBIAS CS C1 12pF 1.0µF AVDD SDOUT XIN SDIO XOUT SCLK DGND DVDD DVDD DGND FIGURE 37.
PAGE 37
REF200 100µA 100µA A B 3 +In 7 5 1 RG R1 100Ω INA118 6 8 R2 100Ω 4 2 –In AINN REFOUT CS C1 12pF XTAL C2 12pF AVDD AGND MODE ADS1210 DRDY DSYNC AGND 1.0µF AVDD VBIAS AGND DVDD DGND REFIN AGND AGND R3 14kΩ AINP DGND SDOUT XIN SDIO XOUT SCLK DGND DVDD DVDD DGND FIGURE 39. PT100 Interface. +15V +In 15 3 4–20mA CT 2 14 RCV420 13 –In 5 1 REFIN AINN REFOUT AGND AGND –15V DVDD AVDD VBIAS CS C1 12pF C2 12pF 1.
PAGE 38
+In 3 7 5 1 RG –In 8 INA128 6 4 2 DVDD CS C1 12pF C2 12pF 1.0µF AVDD +5V AGND MODE ADS1210 DRDY DSYNC XTAL DGND REFOUT VBIAS –5V AGND REFIN AINN AGND AGND R1 10kΩ AINP DGND SDOUT XIN SDIO XOUT SCLK DGND DVDD DVDD DGND FIGURE 42. Dual Supply, High-Accuracy Thermocouple. +In 3 7 RG –In R1 10kΩ INA118 8 2 AGND 5 1 6 4 AGND AIN3N AIN3P AIN2P AIN4N AIN2N AIN4P AIN1P REFIN AIN1N REFOUT AGND AGND 1N4148 AGND VBIAS R2 13kΩ DVDD CS 1.
PAGE 39
3 +In 7 5 1 RG R1 10kΩ INA118 6 8 4 2 –In AIN3N AIN3P AIN2P AIN4N AIN2N AIN4P AIN1P REFIN AIN1N REFOUT AGND –5V AGND AGND AGND R2 13kΩ 1N4148 AGND DVDD +5V AVDD VBIAS MODE CS DRDY AGND DGND C1 12pF SDOUT DSYNC XTAL DGND ADS1211U, P 1.0µF C2 12pF XIN SDIO XOUT SCLK DGND DVDD DVDD DGND FIGURE 44. Dual Supply, High-Accuracy Thermocouple Interface with Cold Junction Compensation.
PAGE 40
TOPIC INDEX TOPIC PAGE FEATURES ..................................................................................... APPLICATIONS ............................................................................. DESCRIPTION ............................................................................... SPECIFICATIONS .......................................................................... TOPIC PAGE 1 ANALOG OPERATION .................................................................
PAGE 41
FIGURE INDEX TABLE INDEX FIGURE TITLE TABLE TITLE Figure 1 Normalized Digital Filter Response ......................................... 11 Table I Full-Scale Range vs PGA Setting ............................................. 9 Figure 2 Digital Filter Response at a Data Rate of 50Hz ..................... 11 Table II Available PGA Settings vs Turbo Mode Rate .......................... 9 Figure 3 Digital Filter Response at a Data Rate of 60Hz .....................
PAGE 42
PACKAGE OPTION ADDENDUM www.ti.
PAGE 43
PACKAGE OPTION ADDENDUM www.ti.com 13-May-2013 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
PAGE 44
PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS1210U/1K SOP ADS1211E/1K ADS1211U/1K SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.9 12.0 2.7 12.0 24.0 Q1 DTC 18 1000 330.0 24.4 SSOP DB 28 1000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 Q1 SOIC DW 24 1000 330.0 24.4 10.75 15.7 2.7 12.0 24.
PAGE 45
PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1210U/1K SOP DTC 18 1000 367.0 367.0 45.0 ADS1211E/1K SSOP DB 28 1000 367.0 367.0 38.0 ADS1211U/1K SOIC DW 24 1000 367.0 367.0 45.
PAGE 46
MECHANICAL DATA MPDS095 – APRIL 2001 DTC (R-PDSO-G18) –A– PLASTIC SMALL-OUTLINE 0.4625 (11,75) C 0°–8° 0.4469 (11,35) 10 18 0.050 (1,27) 0.016 (0,40) D –B– 0.2992 (7,60) 0.2914 (7,40) 0.419 (10,65) 0.394 (10,00) 0.010 (0,25) M B M Index Area 1 9 E E 0.0118 (0,30) 0.004 (0,10) 0.050 (1,27) 0.029 (0,75) 0.010 (0,25) x 45° 0.1043 (2,65) 0.0926 (2,35) Base Plane Seating Plane –C– 0.0125 (0,32) 0.020 (0,51) 0.013 (0,33) 0.010 (0,25) 0.0091 (0,23) 0.
PAGE 47
PAGE 48
PAGE 49
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 50
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.