AD S ADS 121 ADS1212 ADS1213 1212 3 ADS1 212 ADS1 213 ADS1 213 SBAS064B – JANUARY 1996 – REVISED FEBRUARY 2004 22-Bit ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● DELTA-SIGMA A/D CONVERTER ● 22 BITS NO MISSING CODES ● 20 BITS EFFECTIVE RESOLUTION AT 10Hz AND 16 BITS AT 1000Hz ● LOW POWER: 1.
SPECIFICATIONS All specifications TMIN to TMAX, AVDD = DVDD = +5V, fXIN = 1MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REFOUT disabled, VBIAS disabled, and external 2.5V reference, unless otherwise specified.
SPECIFICATIONS (Cont.) All specifications TMIN to TMAX, AVDD = DVDD = +5V, fXIN = 1MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REFOUT disabled, VBIAS disabled, and external 2.5V reference, unless otherwise specified. ADS1212U, P/ADS1213U, P, E PARAMETER CONDITIONS POWER SUPPLY REQUIREMENTS Power Supply Voltage Power Supply Current: Analog Current Digital Current Additional Analog Current with REFOUT Enabled VBIAS Enabled Power Dissipation MIN TYP 4.
ADS1212 SIMPLIFIED BLOCK DIAGRAM AGND AVDD 3 16 REF OUT REF IN VBIAS 17 18 4 +2.5V Reference AINP AINN XOUT 7 +3.
ADS1213 SIMPLIFIED BLOCK DIAGRAM AGND AVDD 6 19 REFIN VBIAS 20 21 7 +2.5V Reference 4 AIN1P REFOUT XIN XOUT 10 +3.
ADS1213E PIN CONFIGURATION TOP VIEW SSOP AIN3N 1 28 AIN3P AIN2P 2 27 AIN4N AIN2N 3 26 AIN4P AIN1P 4 25 REFIN AIN1N 5 24 REFOUT AGND 6 23 AVDD VBIAS 7 NIC 8 NIC 9 CS 10 DSYNC 11 6 ADS1213E PIN DEFINITIONS 22 MODE ADS1213E 21 NIC 20 NIC 19 DRDY 18 SDOUT XIN 12 17 SDIO XOUT 13 16 SCLK DGND 14 15 DVDD PIN NO NAME DESCRIPTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 AIN3N AIN2P AIN2N AIN1P AIN1N AGND VBIAS NIC NIC CS DSYNC XIN XOUT DGND DVDD SCLK SDIO 18 19 20 21 22 23
TYPICAL PERFORMANCE CURVES At TA = +25°C, AVDD = DVDD = +5V, fXIN = 1MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REFOUT disabled, VBIAS disabled, and external 2.5V reference, unless otherwise noted. EFFECTIVE RESOLUTION vs DATA RATE (1MHz Clock) EFFECTIVE RESOLUTION vs DATA RATE (2.
TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, AVDD = DVDD = +5V, fXIN = 1MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REFOUT disabled, VBIAS disabled, and external 2.5V reference, unless otherwise noted. POWER DISSIPATION vs PGA SETTING (REFOUT Enabled) ANALOG CURRENT vs PGA SETTING (REFOUT Enabled) 15 2700 Power Dissipation (mW) 14 13.5 13 12.5 12 11.5 2500 2400 2300 2200 2100 11 2000 10.
THEORY OF OPERATION The ADS1212 and ADS1213 are precision, high dynamic range, self-calibrating, 24-bit, delta-sigma A/D converters capable of achieving very high resolution digital results. Each contains a programmable gain amplifier (PGA); a second-order delta-sigma modulator; a programmable digital filter; a microcontroller including the Instruction, Command and Calibration registers; a serial interface; a clock generator circuit; and an internal 2.5V reference.
DATA RATE (HZ) -3DB FREQUENCY (HZ) G=1 G=2 G=4 G=8 G = 16 10 25 30 50 60 100 250 2.62 6.55 7.86 13.1 15.7 26.2 65.5 20 19 19 17 17 15 12 20 19 19 17 17 15 12 20 19 18 17 17 15 12 19 18 18 17 16 15 12 18 18 17 16 16 15 12 EFFECTIVE RESOLUTION (BITS RMS) TABLE III. Effective Resolution vs Data Rate and Gain Setting. (Turbo Mode Rate of 1 and a 1MHz clock.) DEFINITION OF TERMS An attempt has been made to be consistent with the terminology used in this data sheet.
fXIN—The frequency of the crystal oscillator or CMOS compatible input signal at the XIN input of the ADS1212/13. NORMALIZED DIGITAL FILTER RESPONSE 0 fMOD—The frequency or speed at which the modulator of the ADS1212/13 is running, given by the following equation: f XIN • Turbo Mode 128 fSAMP—The frequency or switching speed of the input sampling capacitor.
Filter Equation The digital filter is described by the following transfer function: π • f • N sin f MOD | H (f ) | = π•f N • sin f MOD 3 In a Turbo Mode Rate of 16, the ADS1212/13 can offer 16 bits of effective resolution at a 1kHz data rate. A comparison of effective resolution versus Turbo Mode Rates and output data rates is shown in Table IV while Table V shows the corresponding noise level in µVrms. where N is the Decimation Ratio.
The Turbo Mode Rate (TMR) is programmed via the Sampling Frequency bits of the Command Register. Due to the increase in input capacitor sampling frequency, higher Turbo Mode settings result in lower analog input impedance; AIN Impedance (Ω) = (1MHz/fXIN)•20E6/(G•TMR) where G is the gain setting.
Normal Mode Valid Data Valid Data Normal Mode Self-Calibration Mode Offset Calibration on Internal Offset(2) Full-Scale Calibration on Internal Full-Scale Analog Input Conversion Valid Data Valid Data DRDY SC(1) Serial I/O tDATA NOTES: (1) SC = Self-Calibration instruction. (2) In Slave Mode, this function requires 4 cycles. FIGURE 5. Self-Calibration Timing.
Normal operation returns within a single conversion cycle because it is assumed that the input voltage at the converter’s input is not removed immediately after the full-scale calibration is performed. In this case, the digital filter already contains a valid result. the input. Conversions proceed as usual over the next three cycles in order to fill the digital filter. DRDY remains HIGH during this time. On the next cycle, the DRDY signal goes LOW indicating valid data and resumption of normal operation.
Also, during this cycle, the sampling capacitor is disconnected from the converter’s analog input and is connected across REFIN. A gain calibration is initiated and proceeds over the next three conversions. After this, the input capacitor is once again connected to the analog input. Conversions proceed as usual over the next three cycles in order to fill the digital filter. DRDY remains HIGH during this time.
considerations associated with VBIAS and the settling of external circuitry. All of these must be taken into account when determining the amount of time required to resume normal operation. The timing diagram shown in Figure 10 does not take into account the settling of external circuitry.
R1 3kΩ ±10V AINP REFIN ±10V AINN REFOUT R2 3kΩ R3 1kΩ R4 1kΩ AGND AVDD VBIAS DVDD C1 6pF GND DGND C2 6pF AVDD AGND MODE ADS1212 DRDY CS DGND DSYNC XTAL 1.0µF SDOUT XIN SDIO XOUT SCLK DGND DVDD DVDD DGND FIGURE 12. ±10V Input Configuration Using VBIAS. The circuitry which generates the +2.5V reference can be disabled via the Command Register and will result in a lower power dissipation. The reference circuitry consumes a little over 1.6mA of current with no external load.
The Command Register (CMR) controls all of the ADS1212/ 13’s options and operating modes. These include the PGA gain setting, the Turbo Mode Rate, the output data rate (decimation ratio), etc. The CMR is the only 32-bit register within the ADS1212/13. It, and all the remaining registers, may be read from or written to. Instruction Register (INSR) The INSR is an 8-bit register which commands the serial interface either to read or to write “n” bytes beginning at the specified register location.
DF (Data Format) Bit—The DF bit controls the format of the output data, either Two’s Complement or Offset Binary, as follows: DF FORMAT ANALOG INPUT DIGITAL OUTPUT SDL SERIAL DATA OUTPUT PIN 0 1 SDIO SDOUT 0 Two’s Complement +Full-Scale Zero –Full-Scale 7FFFFFH 000000H 800000H 1 Offset Binary +Full-Scale Zero –Full-scale FFFFFFH 800000H 000000H Default These two formats are the same for all bits except the most significant, which is simply inverted in one format vs the other.
DATA RATE (HZ) DECIMATION RATIO DR12 DR11 DR10 DR9 DR8 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 391 250 100 60 50 20 10 0.96 19 30 77 129 155 390 780 8000 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 0 1 0 1 1 1 0 0 0 Table XI. Decimation Ratios for Various Data Rates (Turbo Mode Rate of 1 and 1MHz clock).
Offset Calibration Register (OCR) The OCR is a 24-bit register which contains the offset correction factor that is applied to the conversion result before it is placed in the Data Output Register (see Table XIII). In most applications, the contents of this register will be the result of either a self-calibration or a system calibration. The OCR is both readable and writeable via the serial interface.
SYMBOL DESCRIPTION MIN NOM MAX UNITS fXIN XIN Clock Frequency 0.5 1 2.5 MHz tXIN XIN Clock Period 400 XIN Clock High 0.4 • tXIN t3 XIN Clock LOW 0.
t16 DRDY t18 t17 SCLK SDIO IN7 IN1 IN0 INM IN1 IN0 OUT1 OUT0 OUT1 OUT0 Write Register Data IN7 SDIO IN1 IN0 OUTM Read Register Data using SDIO IN7 SDIO IN1 IN0 SDOUT OUTM Read Register Data using SDOUT FIGURE 16. Serial Interface Timing (CS LOW), Master Mode.
DRDY t20 t21 t37 CS t24 t19 t23 SCLK IN7 SDIO IN1 IN0 t24 INM IN1 IN0 IN7 OUTM OUT1 OUT0 IN7 Write Register Data IN7 SDIO IN1 IN0 Read Register Data Using SDIO IN7 SDIO IN1 IN0 IN7 OUTM SDOUT OUT1 OUT0 Read Register Data Using SDOUT DRDY t16 t20 CS SCLK OUTM SDIO OUT1 OUT0 Continuous Read of Data Output Register using SDIO OUTM SDOUT OUT1 OUT0 Continuous Read of Data Output Register using SDOUT FIGURE 19. Serial Interface Timing (Using CS), Slave Mode.
Synchronizing Multiple Converters A negative going pulse on DSYNC can be used to synchronize multiple ADS1212/13s. This assumes that each ADS1212/13 is driven from the same master clock and is set to the same Decimation Ratio and Turbo Mode Rate. The affect that this signal has on data output timing in general is discussed in the Serial Interface section. The concern here is what happens if the DSYNC input is completely asynchronous to this master clock.
For example, Figure 24 shows that just prior to the DRDY signal going LOW, the internal Data Output Register (DOR) is updated. This update involves the Offset Calibration Register (OCR) and the Full-Scale Register (FSR). If the OCR or FSR are being written, their final value may not be correct, and the result placed into the DOR will certainly not be valid. Problems can also arise if certain bits of the Command Register are being changed. Note that reading the Data Output Register is an exception.
Start Reading ADS1212/13 drives DRDY LOW From Read Flowchart Start Writing To Write Flowchart ADS1212/13 drives DRDY LOW CS taken high for 22 t XIN periods minimum (see text if CS tied LOW). CS state HIGH LOW CS state CS state HIGH LOW HIGH Continuous Read Mode? CS taken high for 22 t XIN periods minimum (see text if CS tied low).
Using CS and Continuous Read Mode The serial interface may make use of the CS signal, or this input may simply be tied LOW. There are several issues associated with choosing to do one or the other. The CS signal does not directly control the tri-state condition of the SDOUT or SDIO output. These signals are normally in the tri-state condition. They only become active when serial data is being transmitted from the ADS1212/13.
As with the Master Mode of operation, when using SDIO as edge of the last serial clock cycle of the instruction byte, the SDIO pin will begin its transition from input to output. Between six and eight XIN cycles after this falling edge, the SDIO pin will become an output. This transition may be too fast for some microcontrollers and digital signal processors. If a serial communication does not occur during any conversion period, the ADS1212/13 will continue to operate properly.
Three-Wire Interface Figure 28 shows a three-wire interface with a 8xC32 microprocessor. Note that the Slave Mode is selected and the SDIO pin is being used for input and output. Figure 29 shows a different type of three-wire interface with an 8xC51 microprocessor. Here, the Master Mode is used. The interface signals consist of SDOUT, SDIO, and SCLK. P1.0 8xC32 P1.1 P1.2 AVDD P1.3 P1.4 AINP REFIN AINN REFOUT AGND AGND DVDD CS P1.6 AVDD VBIAS P1.5 1.0µF AGND P1.
Four-Wire Interface Figure 30 shows a four-wire interface with a 8xC32 microprocessor. Again, the Slave Mode is being used. Note that the XIN input can also be controlled. It is possible with some microcontrollers and digital signal processors to produce a continuous serial clock, which could be connected to the XIN input. The frequency of the clock is often settable over some range.
PB7 XIRQ PB6 RESET PB5 PC7 PB4 PC6 AINP REFIN PB3 PC5 AINN REFOUT 68HC11 AVDD PC4 AGND PB1 PC3 VBIAS PB0 PC2 CS PE0 PC1 DSYNC PE1 PC0 PE2 XTAL PB2 AGND C1 6pF XTAL DGND 1.0µF AVDD AGND MODE R1 10kΩ ADS1212 DRDY SDOUT XIN SDIO XOUT SCLK DGND DVDD R2 10kΩ DVDD C2 6pF FIGURE 32. Full Interface with a 68HC11 Microprocessor.
SOURCE CURRENT 30 AIN3N AIN3P AIN2P AIN4N AIN2N AIN4P +5V 25 20 IOUT (mA) –40°C 25°C +5V 85°C AIN1P REFIN AIN1N REFOUT AGND 15 +5V 10 C1 6pF XTAL 0 DGND 0 1 2 3 4 5 MODE CS DRDY DSYNC 5 C2 6pF AVDD ADS1213U, P VBIAS R1 49.9kΩ AVDD +5V SDOUT XIN SDIO XOUT SCLK DGND DVDD REF1004 +2.5V 1.0µF +5V VOH VOH P1 2kΩ 0V +5V DGND VOH (V) FIGURE 34. Source Current vs VOH for SDOUT Under Worst-Case Conditions.
LAYOUT POWER SUPPLIES The ADS1212/13 requires the digital supply (DVDD) to be no greater than the analog supply (AVDD) +0.3V. In the majority of systems, this means that the analog supply must come up first, followed by the digital supply. Failure to observe this condition could cause permanent damage to the ADS1212/13. Inputs to the ADS1212/13, such as SDIO, AIN, or REFIN, should not be present before the analog and digital supplies are on. Violating this condition could cause latch-up.
APPLICATIONS The ADS1212/13 can be used in a broad range of data acquisition tasks. The following application diagrams show the ADS1212 and/or ADS1213 being used for bridge transducer measurements, temperature measurement, and 4-20mA receiver applications. 1/2 OPA1013 AVDD AGND 3kΩ AINP REFIN AINN REFOUT AGND AGND AGND DVDD C1 6pF MODE C2 6pF AGND ADS1212 DRDY DSYNC XTAL DGND VBIAS CS 1.0µF AVDD SDOUT XIN SDIO XOUT SCLK DGND DVDD DVDD DGND FIGURE 37.
REF200 100µA 100µA A B 3 +In 7 5 1 RG INA118 8 R2 100Ω R1 100Ω 4 2 –In 6 REFOUT AGND CS C1 6pF XTAL C2 6pF AVDD AGND MODE ADS1212 DRDY DSYNC AGND 1.0µF AVDD VBIAS DVDD DGND REFIN AINN AGND AGND R3 14kΩ AINP DGND SDOUT XIN SDIO XOUT SCLK DGND DVDD DVDD DGND FIGURE 39. PT100 Interface.
+In 3 7 5 1 RG –In 8 INA128 6 4 2 REFIN AINN REFOUT AGND AGND R1 10kΩ AINP AVDD VBIAS –5V DVDD CS C1 6pF AGND C2 6pF DGND +5V AGND MODE ADS1212 DRDY DSYNC XTAL 1.0µF DGND SDOUT XIN SDIO XOUT SCLK DGND DVDD DVDD DGND FIGURE 42. Dual Supply, High-Accuracy Thermocouple. +In 3 7 RG –In R1 10kΩ INA118 8 2 AGND 5 1 6 4 AGND AIN3N AIN3P AIN2P AIN4N AIN2N AIN4P AIN1P REFIN AIN1N REFOUT AGND AGND 1N4148 AGND VBIAS R2 13kΩ DVDD CS 1.
3 +In 7 5 1 RG R1 10kΩ INA118 6 8 4 2 –In AIN3N AIN3P AIN2P AIN4N AIN2N AIN4P AIN1P REFIN AIN1N REFOUT AGND –5V AGND AGND AGND 1N4148 AGND DVDD AGND MODE CS DRDY DGND C1 6pF DSYNC XTAL DGND +5V AVDD ADS1213U, P VBIAS R2 13kΩ 1.0µF C2 6pF SDOUT XIN SDIO XOUT SCLK DGND DVDD DVDD DGND FIGURE 44. Dual Supply, High-Accuracy Thermocouple Interface with Cold Junction Compensation.
TOPIC INDEX TOPIC PAGE FEATURES ..................................................................................... APPLICATIONS ............................................................................. DESCRIPTION ............................................................................... SPECIFICATIONS .......................................................................... TOPIC PAGE 1 ANALOG OPERATION .................................................................
FIGURE INDEX TABLE INDEX FIGURE TITLE TABLE TITLE Figure 1 Normalized Digital Filter Response ......................................... 11 Table I Full-Scale Range vs PGA Setting ............................................. 9 Figure 2 Digital Filter Response at a Data Rate of 50Hz ..................... 11 Table II Available PGA Settings vs Turbo Mode Rate .......................... 9 Figure 3 Digital Filter Response at a Data Rate of 60Hz .....................
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS1212U/1K SOP ADS1213E/1K ADS1213U/1K SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.9 12.0 2.7 12.0 24.0 Q1 DTC 18 1000 330.0 24.4 SSOP DB 28 1000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 Q1 SOIC DW 24 1000 330.0 24.4 10.75 15.7 2.7 12.0 24.
PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1212U/1K SOP DTC 18 1000 367.0 367.0 45.0 ADS1213E/1K SSOP DB 28 1000 367.0 367.0 38.0 ADS1213U/1K SOIC DW 24 1000 367.0 367.0 45.
MECHANICAL DATA MPDS095 – APRIL 2001 DTC (R-PDSO-G18) –A– PLASTIC SMALL-OUTLINE 0.4625 (11,75) C 0°–8° 0.4469 (11,35) 10 18 0.050 (1,27) 0.016 (0,40) D –B– 0.2992 (7,60) 0.2914 (7,40) 0.419 (10,65) 0.394 (10,00) 0.010 (0,25) M B M Index Area 1 9 E E 0.0118 (0,30) 0.004 (0,10) 0.050 (1,27) 0.029 (0,75) 0.010 (0,25) x 45° 0.1043 (2,65) 0.0926 (2,35) Base Plane Seating Plane –C– 0.0125 (0,32) 0.020 (0,51) 0.013 (0,33) 0.010 (0,25) 0.0091 (0,23) 0.
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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