Datasheet

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SINC
3
FILTER RESPONSE
(1)
(
−
3dB = 0.262
•
f
DATA
= 15.76Hz)
Frequency (Hz)
0
−
20
−
40
−
60
−
80
−
100
−
120
0 30 12060 90 150 180 210 240 270 300
Gain (dB)
SINC
2
FILTER RESPONSE
(1)
(
−
3dB = 0.318
•
f
DATA
= 19.11Hz)
Frequency (Hz)
0
−
20
−
40
−
60
−
80
−
100
−
120
0 30 12060 90 150 180 210 240 270 300
Gain (dB)
FAST SETTLING FILTER RESPONSE
(1)
(
−
3dB = 0.469
•
f
DATA
= 28.125Hz)
Frequency (Hz)
0
−
20
−
40
−
60
−
80
−
100
−
120
0
NOTE: (1) f
DATA
= 60Hz.
30 12060 90 150 180 210 240 270 300
Gain (dB)
DIGITAL I/O INTERFACE SERIAL PERIPHERAL INTERFACE
Chip Select ( CS)
ADS1218
SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005
Figure 28. Filter Frequency Responses
The ADS1218 has eight pins dedicated for digital I/O. The Serial Peripheral Interface (SPI) allows a
The default power-up condition for the digital I/O pins controller to communicate synchronously with the
are as inputs. All of the digital I/O pins are individually ADS1218. The ADS1218 operates in slave-only
configurable as inputs or outputs. They are mode.
configured through the DIR control register. The DIR
register defines whether the pin is an input or output,
and the DIO register defines the state of the digital
The chip select ( CS) input of the ADS1218 must be
output. When the digital I/O are configured as inputs,
externally asserted before a master device can
DIO is used to read the state of the pin. If the digital
exchange data with the ADS1218. CS must be low
I/O are not used, either 1) configure as outputs; or 2)
for the duration of the transaction. CS can be tied
leave as inputs and tie to ground; this prevents
low.
excess power dissipation.
19