Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- ELECTRICAL CHARACTERISTICS: AVDD = 5V
- ELECTRICAL CHARACTERISTICS: AVDD = 3V
- DIGITAL CHARACTERISTICS: TMIN to TMAX, DVDD = 2.7V to 5.25V
- FLASH CHARACTERISTICS: TMIN to TMAX, DVDD = 2.7V to 5.25V, unless otherwise specified.
- PIN CONFIGURATION
- TIMING SPECIFICATIONS
- TIMING SPECIFICATION TABLE
- TIMING SPECIFICATION TABLE
- TYPICAL CHARACTERISTICS
- OVERVIEW
- INPUT MULTIPLEXER
- TEMPERATURE SENSOR
- BURNOUT CURRENT SOURCES
- INPUT BUFFER
- IDAC1 AND IDAC2
- PGA
- PGA OFFSET DAC
- MODULATOR
- VOLTAGE REFERENCE INPUT
- ON-CHIP VOLTAGE REFERENCE
- VRCAP PIN
- CLOCK GENERATOR
- CALIBRATION
- DIGITAL FILTER
- DIGITAL I/O INTERFACE
- SERIAL PERIPHERAL INTERFACE
- DATA READY
- DSYNC OPERATION
- MEMORY
- REGISTER BANK
- RAM
- FLASH
- REGISTER MAP
- COMMAND DEFINITIONS

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D
IN
0000 1111
D
IN
0001 0001 0000 0001 xxxx xxxx xxxx xxxx
D
OUT
MUX ACR
• • •
(1)
D
IN
0010 0010 x000 0001 xxxx xxxx xxxx xxxx
D
OUT
RAM Data
20
H
RAM Data
21
H
• • •
(1)
ADS1218
SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005
STOPC Stop Continuous
Description: Ends the continuous data output mode.
Operands: None
Bytes: 1
Encoding: 0000 1111
Data Transfer Sequence:
RREG Read from Registers
Description: Output the data from up to 16 registers starting with the register address specified as part of the
instruction. The number of registers read will be one plus the second byte. If the count exceeds the remaining
registers, the addresses will wrap back to the beginning.
Operands: r, n
Bytes: 2
Encoding: 0001 rrrr xxxx nnnn
Data Transfer Sequence:
Read Two Registers Starting from Register 01
H
(MUX)
NOTE: (1) For wait time, refer to timing specification.
RRAM Read from RAM
Description: Up to 128 bytes can be read from RAM starting at the bank specified in the op code. All reads start
at the address for the beginning of the RAM bank. The number of bytes to read will be one plus the value of the
second byte.
Operands: a, n
Bytes: 2
Encoding: 0010 0aaa xnnn nnnn
Data Transfer Sequence:
Read Two RAM Locations Starting from 20
H
NOTE: (1) For wait time, refer to timing specification.
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