Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- ELECTRICAL CHARACTERISTICS: AVDD = 5V
- ELECTRICAL CHARACTERISTICS: AVDD = 3V
- DIGITAL CHARACTERISTICS: TMIN to TMAX, DVDD = 2.7V to 5.25V
- FLASH CHARACTERISTICS: TMIN to TMAX, DVDD = 2.7V to 5.25V, unless otherwise specified.
- PIN CONFIGURATION
- TIMING SPECIFICATIONS
- TIMING SPECIFICATION TABLE
- TIMING SPECIFICATION TABLE
- TYPICAL CHARACTERISTICS
- OVERVIEW
- INPUT MULTIPLEXER
- TEMPERATURE SENSOR
- BURNOUT CURRENT SOURCES
- INPUT BUFFER
- IDAC1 AND IDAC2
- PGA
- PGA OFFSET DAC
- MODULATOR
- VOLTAGE REFERENCE INPUT
- ON-CHIP VOLTAGE REFERENCE
- VRCAP PIN
- CLOCK GENERATOR
- CALIBRATION
- DIGITAL FILTER
- DIGITAL I/O INTERFACE
- SERIAL PERIPHERAL INTERFACE
- DATA READY
- DSYNC OPERATION
- MEMORY
- REGISTER BANK
- RAM
- FLASH
- REGISTER MAP
- COMMAND DEFINITIONS
www.ti.com
D
IN
1100 0000
D
IN
1101 0011
• • •
(1)
xxxx xxxx
D
OUT
Checksum
D
IN
1101 1000
• • •
(1)
xxxx xxxx
D
OUT
Checksum
ADS1218
SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005
CRAM Copy RAM Bank to Registers
Description: Copy the selected RAM Bank to the Configuration Registers. This will overwrite all of the registers
with the data from the RAM bank.
Operands: a
Bytes: 1
Encoding: 1100 0aaa
Data Transfer Sequence:
Copy RAM Bank 0 to the Registers
CSRAMX Calculate RAM Bank Checksum
Description: Calculate the checksum of the selected RAM Bank. The checksum is calculated as a sum of all the
bytes with the carry ignored. The ID, DRDY, and DIO bits are masked so they are not included in the checksum.
Operands: a
Bytes: 1
Encoding: 1101 0aaa
Data Transfer Sequence:
Calculate Checksum for RAM Bank 3
NOTE: (1) For wait time, refer to timing specification.
CSARAMX Calculate the Checksum for all RAM Banks
Description: Calculate the checksum of all RAM Banks. The checksum is calculated as a sum of all the bytes
with the carry ignored. The ID, DRDY, and DIO bits are masked so they are not included in the checksum.
Operands: None
Bytes: 1
Encoding: 1101 1000
Data Transfer Sequence:
NOTE: (1) For wait time, refer to timing specification.
32