Datasheet

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24-Bit

ANALOG-TO-DIGITAL CONVERTER

FEATURES

● 24 BITS NO MISSING CODES

● SIMULTANEOUS 50Hz AND 60Hz REJECTION

(–90dB MINIMUM)

● 0.0015% INL

● 21 BITS EFFECTIVE RESOLUTION

(PGA = 1), 19 BITS (PGA = 128)

● PGA GAINS FROM 1 TO 128

● SINGLE CYCLE SETTLING

● PROGRAMMABLE DATA OUTPUT RATES

● EXTERNAL DIFFERENTIAL REFERENCE

OF 0.1V TO 5V

● ON-CHIP CALIBRATION

● SPI™ COMPATIBLE

● 2.7V TO 5.25V SUPPLY RANGE

● 600µW POWER CONSUMPTION

● UP TO EIGHT INPUT CHANNELS

● UP TO EIGHT DATA I/O

DESCRIPTION

The ADS1240 and ADS1241 are precision, wide dynamic range,

delta-sigma, Analog-to-Digital (A/D) converters with 24-bit resolution

operating from 2.7V to 5.25V power supplies. The delta-sigma A/D

converter provides up to 24 bits of no missing code performance and

effective resolution of 21 bits.

The input channels are multiplexed. Internal buffering can be

selected to provide very high input impedance for direct connection

to transducers or low-level voltage signals. Burnout current sources

are provided that allow for detection of an open or shorted sensor.

An 8-bit Digital-to-Analog (D/A) converter provides an offset cor-

rection with a range of 50% of the Full-Scale Range (FSR).

The Programmable Gain Amplifier (PGA) provides selectable gains of

1 to 128, with an effective resolution of 19 bits at a gain of 128. The

A/D conversion is accomplished with a 2nd-order delta-sigma modu-

lator and programmable Finite-Impulse Response (FIR) filter that

provides a simultaneous 50Hz and 60Hz notch. The reference input

is differential and can be used for ratiometric conversion.

The serial interface is SPI compatible. Up to eight bits of data

I/O are also provided that can be used for input or output. The

ADS1240 and ADS1241 are designed for high-resolution measure-

ment applications in smart transmitters, industrial process control,

weigh scales, chromatography, and portable instrumentation.

APPLICATIONS

● INDUSTRIAL PROCESS CONTROL

● WEIGH SCALES

● LIQUID/GAS CHROMATOGRAPHY

● BLOOD ANALYSIS

● SMART TRANSMITTERS

● PORTABLE INSTRUMENTATION

BUF PGA

A = 1:128

Clock Generator

Serial Interface

2nd-Order

Modulator

AGNDAV

REF+

REF–

OUT

DSYNCPDWN RESET DRDYBUFEN DGNDDV

SCLK

POL

OUT

MUX

0/D0

1/D1

2/D2

3/D3

4/D4

5/D5

6/D6

7/D7

INCOM

Controller Registers

Digital

Filter

2µA

Offset

DAC

AGND

2µA

ADS1241

Only

ADS1240

ADS1241

SBAS173F – JUNE 2001 – REVISED OCTOBER 2013

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks property of their respective owners.

Summary of content (29 pages)

PAGE 1
ADS1240 ADS1241 ADS 124 0 ADS 124 1 SBAS173F – JUNE 2001 – REVISED OCTOBER 2013 24-Bit ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● 24 BITS NO MISSING CODES ● SIMULTANEOUS 50Hz AND 60Hz REJECTION (–90dB MINIMUM) ● 0.0015% INL ● 21 BITS EFFECTIVE RESOLUTION (PGA = 1), 19 BITS (PGA = 128) ● PGA GAINS FROM 1 TO 128 ● SINGLE CYCLE SETTLING ● PROGRAMMABLE DATA OUTPUT RATES ● EXTERNAL DIFFERENTIAL REFERENCE OF 0.1V TO 5V ● ON-CHIP CALIBRATION ● SPI™ COMPATIBLE ● 2.7V TO 5.
PAGE 2
ABSOLUTE MAXIMUM RATINGS(1) AVDD to DGND ...................................................................... –0.3V to +6V DVDD to DGND ...................................................................... –0.3V to +6V Input Current ............................................................... 100mA, Momentary DGND to AGND .................................................................... –0.3V to 0.3V Input Current .................................................................
PAGE 3
ELECTRICAL CHARACTERISTICS: AVDD = 5V All specifications TMIN to TMAX, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, fDATA = 15Hz, and VREF = +2.5V, unless otherwise specified. ADS1240 ADS1241 PARAMETER ANALOG INPUT (AIN0 – AIN7, AINCOM) Analog Input Range Full-Scale Input Range Differential Input Impedance Bandwidth fDATA = 3.75Hz fDATA = 7.50Hz fDATA = 15.
PAGE 4
ELECTRICAL CHARACTERISTICS: AVDD = 3V All specifications –40°C to +85°C, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, fDATA = 15Hz, and VREF = +1.25V, unless otherwise specified. ADS1240 ADS1241 PARAMETER ANALOG INPUT (AIN0 – AIN7, AINCOM) Analog Input Range Full-Scale Input Voltage Range Input Impedance Differential Bandwidth fDATA = 3.75Hz fDATA = 7.50Hz fDATA = 15.
PAGE 5
PIN CONFIGURATION (ADS1240) PIN CONFIGURATION (ADS1241) Top View SSOP Top View SSOP DVDD 1 28 BUFEN DGND 2 27 DRDY DVDD 1 24 BUFEN DGND 2 23 DRDY XIN 3 26 SCLK XIN 3 22 SCLK XOUT 4 25 DOUT XOUT 4 21 DOUT RESET 5 24 DIN RESET 5 20 DIN DSYNC 6 23 CS DSYNC 6 19 CS PDWN 7 ADS1240 22 POL ADS1241 PDWN 7 18 POL DGND 8 DGND 8 17 AVDD VREF+ 9 20 AGND VREF+ 9 16 AGND VREF– 10 19 AINCOM VREF– 10 15 AINCOM AIN0/D0 11 18 AIN3/D3 AIN0/D0 11 14 AIN3/D3 AI
PAGE 6
TIMING DIAGRAMS CS t3 t1 t2 t10 SCLK (POL = 0) SCLK (POL = 1) t4 DIN t2 t6 t5 MSB t11 LSB t7 (Command or Command and Data) t8 DOUT t9 MSB(1) LSB(1) NOTE: (1) Bit order = 0. ADS1240 or ADS1241 Resets On Falling Edge 300 • tOSC < t12 < 500 • tOSC SCLK Reset Waveform t13 t13 t13 : > 5 • tOSC 550 • tOSC < t14 < 750 • tOSC SCLK t12 t14 1050 • tOSC < t15 < 1250 • tOSC t15 DIAGRAM 1. t16 tDATA DRDY RESET, DSYNC, PDWN t17 t18 SCLK t19 DIAGRAM 2.
PAGE 7
TYPICAL CHARACTERISTICS All specifications AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified. EFFECTIVE NUMBER OF BITS vs PGA SETTING EFFECTIVE NUMBER OF BITS vs PGA SETTING 22 21.5 DR = 10 21.0 21 DR = 10 DR = 01 20 20.0 ENOB (rms) ENOB (rms) 20.5 19.5 19.0 DR = 00 18.5 19 DR = 01 18 DR = 00 17 18.0 Buffer ON Buffer OFF 16 17.5 15 17.
PAGE 8
TYPICAL CHARACTERISTICS (Cont.) All specifications AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified. GAIN vs TEMPERATURE (Cal at 25°C) OFFSET vs TEMPERATURE (Cal at 25°C) 1.00010 50 PGA16 PGA1 1.00006 Gain (Normalized) Offset (ppm of FS) 0 –50 PGA64 –100 PGA128 –150 1.00002 0.99998 0.99994 0.99990 0.
PAGE 9
TYPICAL CHARACTERISTICS (Cont.) All specifications AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified. OFFSET DAC OFFSET vs TEMPERATURE (Cal at 25°C) NOISE HISTOGRAM Number of Occurrences 3000 200 10k Readings VIN = 0V 170 140 Offset (ppm of FSR) 3500 2500 2000 1500 1000 110 80 50 20 –10 –40 500 –70 –100 0 –50 –30 –10 –3.5 –3.0 –2.5 –2.0 –1.5 –1 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.
PAGE 10
OVERVIEW INPUT MULTIPLEXER The input multiplexer provides for any combination of differential inputs to be selected on any of the input channels, as shown in Figure 1.
PAGE 11
The buffer draws additional current when activated. The current required by the buffer depends on the PGA setting. When the PGA is set to 1, the buffer uses approximately 50µA; when the PGA is set to 128, the buffer uses approxi- AVDD 2µA mately 500µA. AVDD ADC OPEN CIRCUIT CODE = 0x7FFFFFH 0V 2µA FIGURE 3. Burnout detection while sensor is open-circuited. Figure 4 shows a short-circuited sensor.
PAGE 12
SELFGCAL. Afterwards set PGA = 64 and issue SELFOCAL. For operation with a reference voltage greater than (AVDD – 1.5) volts, the buffer must also be turned off during gain selfcalibration to avoid exceeding the buffer input range. System calibration corrects both internal and external offset and gain errors. While performing system calibration, the appropriate signal must be applied to the inputs.
PAGE 13
ADS1240 AND ADS1241 FILTER RESPONSE WHEN fDATA = 15Hz FREQUENCY RESPONSE FROM 45Hz to 65Hz WHEN fDATA = 15Hz 0 –40 –20 –50 –40 –60 Magnitude (dB) Gain (dB) –60 –80 –100 –120 –140 –90 –100 –110 –130 –180 –140 0 20 40 60 80 100 120 140 160 180 200 45 50 55 60 Frequency (Hz) Frequency (Hz) ADS1240 AND ADS1241 FILTER RESPONSE WHEN fDATA = 7.5Hz FREQUENCY RESPONSE FROM 45Hz to 65Hz WHEN fDATA = 7.
PAGE 14
logic one or zero when configured as an input to prevent excess current dissipation. If the pin is configured as an output in the DIR register, then the corresponding DIO register bit value determines the state of the output pin (0 = AGND, 1 = AVDD). Data Continuous Mode (RDATAC) command should not be issued when DIN and DOUT are connected. While in RDATAC mode, DIN looks for the STOPC or RESET command. If either of these 8-bit bytes appear on DOUT (which is connected to DIN), the RDATAC mode ends.
PAGE 15
ADS1240 AND ADS1241 REGISTER tion needed to configure the part, such as data format, multiplexer settings, calibration settings, data rate, etc. The set of the 16 registers are shown in Table III. The operation of the device is set up through individual registers.
PAGE 16
ODAC (Address 03 ) Offset DAC Reset Value = 00H ACR (Address 02H) Analog Control Register Reset Value = X0H bit 7 bit 6 bit 5 bit 4 DRDY U/B SPEED BUFEN bit 3 bit 2 BIT ORDER RANGE bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DR1 DR0 SIGN OSET6 OSET5 OSET4 OSET3 OSET2 OSET1 OSET0 bit 7 DRDY: Data Ready (Read Only) This bit duplicates the state of the DRDY pin.
PAGE 17
OCR1 (Address 08H) Offset Calibration Coefficient (Middle Byte) Reset Value = 00H FSR2 (Address 0CH) Full-Scale Register (Most Significant Byte) Reset Value = 55H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 OCR15 OCR14 OCR13 OCR12 OCR11 OCR10 OCR09 OCR08 FSR23 FSR22 FSR21 FSR20 FSR19 FSR18 FSR17 FSR16 OCR2 (Address 09H) Offset Calibration Coefficient (Most Significant Byte) Reset Value = 00H DOR2 (Address 0DH) Data Output
PAGE 18
ADS1240 AND ADS1241 CONTROL COMMAND DEFINITIONS The commands listed in Table IV control the operations of the ADS1240 and ADS1241. Some of the commands are stand-alone commands (e.g., RESET) while others require additional bytes (e.g., WREG requires the count and data bytes).
PAGE 19
STOPC–Stop Continuous SELFCAL–Offset and Gain Self Calibration Description: Ends the continuous data output mode. Issue after DRDY goes LOW. Operands: None Description: Starts the process of self calibration. The Offset Calibration Register (OCR) and the Full-Scale Register (FSR) are updated with new values after this operation.
PAGE 20
SYSOCAL–System Offset Calibration DSYNC–Sync DRDY Description: Initiates a system offset calibration. The input should be set to 0V, and the ADS1240 and ADS1241 compute the OCR value that compensates for offset errors. The Offset Calibration Register (OCR) is updated after this operation. The user must apply a zero input signal to the appropriate analog inputs. The OCR register is automatically updated afterwards. Description: Synchronizes the ADS1240 and ADS1241 to an external event.
PAGE 21
APPLICATION EXAMPLES output can be directly applied to the differential inputs of ADS1240. GENERAL-PURPOSE WEIGH SCALE HIGH PRECISION WEIGH SCALE Figure 8 shows a typical schematic of a general-purpose weigh scale application using the ADS1240. In this example, the internal PGA is set to either 64 or 128 (depending on the maximum output voltage of the load cell) so that the load cell Figure 9 shows the typical schematic of a high-precision weigh scale application using the ADS1240.
PAGE 22
fMOD = DEFINITION OF TERMS An attempt has been made to be consistent with the terminology used in this data sheet. In that regard, the definition of each term is given as follows: fSAMP—the frequency, or switching speed, of the input samPGA SETTING Analog Input Voltage—the voltage at any one analog input relative to AGND. Analog Input Differential Voltage—given by the following equation: (IN+) – (IN–).
PAGE 23
Revision History DATE REVISION PAGE SECTION 10/13 F 21 Application Examples 8/06 E 6 Timing Characteristics Table DESCRIPTION Changed Figure 9; switched plus and minus in upper op amp. Clarified t10 specification. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. ADS1240, 1241 SBAS173F www.ti.
PAGE 24
PACKAGE OPTION ADDENDUM www.ti.
PAGE 25
PACKAGE OPTION ADDENDUM www.ti.com (4) 7-Oct-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
PAGE 26
PACKAGE MATERIALS INFORMATION www.ti.com 7-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS1240E/1K SSOP DB 24 1000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1 ADS1241E/1K SSOP DB 28 1000 330.0 16.4 8.1 10.4 2.5 12.0 16.
PAGE 27
PACKAGE MATERIALS INFORMATION www.ti.com 7-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1240E/1K SSOP DB 24 1000 367.0 367.0 38.0 ADS1241E/1K SSOP DB 28 1000 367.0 367.0 38.
PAGE 28
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 29
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