Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External TSSOP 16

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

24-Bit

ANALOG-TO-DIGITAL CONVERTER

FEATURES

● 24 BITS NO MISSING CODES

● SIMULTANEOUS 50Hz AND 60Hz REJECTION

(–90dB MINIMUM)

● 0.0015% INL

● 21 BITS EFFECTIVE RESOLUTION

(PGA = 1), 19 BITS (PGA = 128)

● PGA GAINS FROM 1 TO 128

● SINGLE-CYCLE SETTLING

● PROGRAMMABLE DATA OUTPUT RATES

● EXTERNAL DIFFERENTIAL REFERENCE

OF 0.1V TO 5V

● ON-CHIP CALIBRATION

● SPI™ COMPATIBLE

● 2.7V TO 5.25V SUPPLY RANGE

● 600µW POWER CONSUMPTION

● UP TO EIGHT INPUT CHANNELS

● UP TO EIGHT DATA I/O

DESCRIPTION

The ADS1242 and ADS1243 are precision, wide dynamic

range, delta-sigma, analog-to-digital (A/D) converters with

24-bit resolution operating from 2.7V to 5.25V supplies.

These delta-sigma, A/D converters provide up to 24 bits of no

missing code performance and effective resolution of 21 bits.

The input channels are multiplexed. Internal buffering can be

selected to provide a very high input impedance for direct

connection to transducers or low-level voltage signals. Burn-

out current sources are provided that allow for the detection

of an open or shorted sensor. An 8-bit digital-to-analog

converter (DAC) provides an offset correction with a range of

50% of the FSR (Full-Scale Range).

The Programmable Gain Amplifier (PGA) provides selectable

gains of 1 to 128 with an effective resolution of 19 bits at a gain

of 128. The A/D conversion is accomplished with a second-order

delta-sigma modulator and programmable FIR filter that pro-

vides a simultaneous 50Hz and 60Hz notch. The reference input

is differential and can be used for ratiometric conversion.

The serial interface is SPI compatible. Up to eight bits of data

I/O are also provided that can be used for input or output. The

ADS1242 and ADS1243 are designed for high-resolution

measurement applications in smart transmitters, industrial

process control, weight scales, chromatography, and portable

instrumentation.

APPLICATIONS

● INDUSTRIAL PROCESS CONTROL

● LIQUID/GAS CHROMATOGRAPHY

● BLOOD ANALYSIS

● SMART TRANSMITTERS

● PORTABLE INSTRUMENTATION

● WEIGHT SCALES

ADS1242

ADS1243

SBAS235H – DECEMBER 2001 – REVISED OCTOBER 2013

www.ti.com

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

BUF PGA

A = 1:128

Clock Generator

Serial Interface

2nd-Order

Modulator

GND

IN+

IN–

REF+

REF–

OUT

PDWN DRDY

SCLK

OUT

MUX

0/D0

1/D1

2/D2

3/D3

4/D4

5/D5

6/D6

7/D7

Controller Registers

Digital

Filter

2µA

Offset

DAC

GND

2µA

ADS1243

Only

All trademarks are the property of their respective owners.

Summary of content (32 pages)

PAGE 1
ADS 124 ® ADS 2 124 ADS1242 ADS1243 ® 3 SBAS235H – DECEMBER 2001 – REVISED OCTOBER 2013 24-Bit ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● 24 BITS NO MISSING CODES ● SIMULTANEOUS 50Hz AND 60Hz REJECTION (–90dB MINIMUM) ● 0.0015% INL ● 21 BITS EFFECTIVE RESOLUTION (PGA = 1), 19 BITS (PGA = 128) ● PGA GAINS FROM 1 TO 128 ● SINGLE-CYCLE SETTLING ● PROGRAMMABLE DATA OUTPUT RATES ● EXTERNAL DIFFERENTIAL REFERENCE OF 0.1V TO 5V ● ON-CHIP CALIBRATION ● SPI™ COMPATIBLE ● 2.7V TO 5.
PAGE 2
ABSOLUTE MAXIMUM RATINGS(1) VDD to GND ........................................................................... –0.3V to +6V Input Current ............................................................... 100mA, Momentary Input Current ................................................................. 10mA, Continuous AIN .................................................................... GND – 0.5V to VDD + 0.5V Digital Input Voltage to GND ...................................... –0.3V to VDD + 0.
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ELECTRICAL CHARACTERISTICS: VDD = 5V All specifications TMIN to TMAX, VDD = +5V, fMOD = 19.2kHz, PGA = 1, Buffer ON, fDATA = 15Hz, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified. ADS1242 ADS1243 PARAMETER ANALOG INPUT (AIN0 – AIN7) Analog Input Range Full-Scale Input Range Differential Input Impedance Bandwidth fDATA = 3.75Hz fDATA = 7.50Hz fDATA = 15.
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ELECTRICAL CHARACTERISTICS: VDD = 3V All specifications TMIN to TMAX, VDD = +3V, fMOD = 19.2kHz, PGA = 1, Buffer ON, fDATA = 15Hz, VREF ≡ (REF IN+) – (REF IN–) = +1.25V, unless otherwise specified. ADS1242 ADS1243 PARAMETER ANALOG INPUT (AIN0 – AIN7) Analog Input Range Full-Scale Input Voltage Range Input Impedance Bandwidth fDATA = 3.75Hz fDATA = 7.50Hz fDATA = 15.
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PIN CONFIGURATION (ADS1242) PIN CONFIGURATION (ADS1243) Top View TSSOP Top View TSSOP VDD 1 20 DRDY VDD 1 16 DRDY XIN 2 19 SCLK XIN 2 15 SCLK XOUT 3 18 DOUT XOUT 3 14 DOUT PDWN 4 17 DIN PDWN 4 VREF+ 5 VREF– 6 15 GND 13 DIN 16 CS ADS1243 ADS1242 VREF+ 5 12 CS VREF– 6 11 GND AIN0/D0 7 14 AIN3/D3 AIN0/D0 7 10 AIN3/D3 AIN1/D1 8 13 AIN2/D2 AIN1/D1 8 9 AIN4/D4 9 12 AIN7/D7 AIN5/D5 10 11 AIN6/D6 AIN2/D2 PIN DESCRIPTIONS (ADS1243) PIN DESCRIPTIONS (ADS124
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TIMING DIAGRAMS CS t3 t1 t2 t10 SCLK t4 DIN MSB t2 t6 t5 t11 LSB t7 (Command or Command and Data) t8 DOUT t9 MSB(1) LSB(1) NOTE: (1) Bit order = 0. ADS1242 or ADS1243 Resets On Falling Edge 300 • tOSC < t12 < 500 • tOSC SCLK Reset Waveform t13 t13 t13 : > 5 • tOSC 550 • tOSC < t14 < 750 • tOSC SCLK t12 t14 1050 • tOSC < t15 < 1250 • tOSC t15 DIAGRAM 1. t16 tDATA DRDY PDWN t17 t18 SCLK t19 DIAGRAM 2.
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TYPICAL CHARACTERISTICS All specifications VDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified. EFFECTIVE NUMBER OF BITS vs PGA SETTING EFFECTIVE NUMBER OF BITS vs PGA SETTING 21.5 22 DR = 10 21.0 21 DR = 10 DR = 01 20 20.0 ENOB (rms) ENOB (rms) 20.5 19.5 19.0 DR = 00 18.5 19 DR = 01 18 DR = 00 17 18.0 Buffer ON Buffer OFF 16 17.5 15 17.
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TYPICAL CHARACTERISTICS (Cont.) All specification VDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified. GAIN vs TEMPERATURE (Cal at 25°C) OFFSET vs TEMPERATURE (Cal at 25°C) 1.00010 50 PGA16 PGA1 1.00006 Gain (Normalized) Offset (ppm of FS) 0 –50 PGA64 –100 PGA128 –150 1.00002 0.99998 0.99994 0.99990 0.
PAGE 9
TYPICAL CHARACTERISTICS (Cont.) All specification VDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified. OFFSET DAC OFFSET vs TEMPERATURE (Cal at 25°C) NOISE HISTOGRAM Number of Occurrences 3000 200 10k Readings VIN = 0V 170 140 Offset (ppm of FSR) 3500 2500 2000 1500 1000 110 80 50 20 –10 –40 500 –70 –100 0 –50 –3.5 –3.0 –2.5 –2.0 –1.5 –1 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.
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OVERVIEW INPUT MULTIPLEXER The input multiplexer provides for any combination of differential inputs to be selected on any of the input channels, as shown in Figure 1. For example, if AIN0 is selected as the positive differential input channel, any other channel can be selected as the negative terminal for the differential input AIN0/D0 AIN1/D1 VDD channel.
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current required by the buffer depends on the PGA setting. When the PGA is set to 1, the buffer uses approximately 50µA; when the PGA is set to 128, the buffer uses approxi- VDD mately 500µA. 2µA VDD PGA ADC OPEN CIRCUIT CODE = 0x7FFFFFH 0V 2µA FIGURE 3. Burnout detection while sensor is open-circuited. shorted and at the same potential, the ADS1242/43 signal outputs are approximately zero.
PAGE 12
example, if using PGA = 64, first set PGA = 1 and issue SELFGCAL. Afterwards, set PGA = 64 and issue SELFOCAL. For operation with a reference voltage greater than (VDD – 1.5) volts, the buffer must also be turned off during gain self-calibration to avoid exceeding the buffer input range. System calibration corrects both internal and external offset and gain errors. While performing system calibration, the appropriate signal must be applied to the inputs.
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ADS1242 AND ADS1243 FILTER RESPONSE WHEN fDATA = 15Hz FREQUENCY RESPONSE FROM 45Hz to 65Hz WHEN fDATA = 15Hz 0 –40 –20 –50 –40 –60 Magnitude (dB) Gain (dB) –60 –80 –100 –120 –140 –90 –100 –110 –130 –180 –140 0 20 40 60 80 100 120 140 160 180 200 45 50 55 60 Frequency (Hz) Frequency (Hz) ADS1242 AND ADS1243 FILTER RESPONSE WHEN fDATA = 7.5Hz FREQUENCY RESPONSE FROM 45Hz to 65Hz WHEN fDATA = 7.
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excess current dissipation. If the pin is configured as an output in the DIR register, then the corresponding DIO register bit value determines the state of the output pin (0 = GND, 1 = VDD). It is still possible to perform A/D conversions on a pin configured as data I/O. This may be useful as a test mode, where the data I/O pin is driven and an A/D conversion is done on the pin.
PAGE 15
ADS1242 AND ADS1243 REGISTERS The operation of the device is set up through individual registers. Collectively, the registers contain all the information needed to configure the part, such as data format, ADDRESS REGISTER BIT 7 BIT 6 BIT 5 multiplexer settings, calibration settings, data rate, etc. The 16 registers are shown in Table III.
PAGE 16
ODAC (Address 03 ) Offset DAC Reset Value = 00H ACR (Address 02H) Analog Control Register Reset Value = X0H bit 7 bit 6 bit 5 bit 4 DRDY U/B SPEED BUFEN bit 3 bit 2 BIT ORDER RANGE bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DR1 DR0 SIGN OSET6 OSET5 OSET4 OSET3 OSET2 OSET1 OSET0 bit 7 DRDY: Data Ready (Read Only) This bit duplicates the state of the DRDY pin.
PAGE 17
OCR1 (Address 08H) Offset Calibration Coefficient (Middle Byte) Reset Value = 00H FSR2 (Address 0CH) Full-Scale Register (Most Significant Byte) Reset Value = 55H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 OCR15 OCR14 OCR13 OCR12 OCR11 OCR10 OCR09 OCR08 FSR23 FSR22 FSR21 FSR20 FSR19 FSR18 FSR17 FSR16 OCR2 (Address 09H) Offset Calibration Coefficient (Most Significant Byte) Reset Value = 00H DOR2 (Address 0DH) Data Output
PAGE 18
ADS1242 AND ADS1243 CONTROL COMMAND DEFINITIONS The commands listed in Table IV control the operations of the ADS1242 and ADS1243. Some of the commands are stand-alone commands (for example, RESET) while others require additional bytes (for example, WREG requires the count and data bytes).
PAGE 19
STOPC–Stop Continuous SELFCAL–Offset and Gain Self Calibration Description: Ends the continuous data output mode. Issue after DRDY goes LOW. Operands: None Description: Starts the process of self calibration. The Offset Calibration Register (OCR) and the Full-Scale Register (FSR) are updated with new values after this operation.
PAGE 20
SYSOCAL–System Offset Calibration DSYNC–Sync DRDY Description: Initiates a system offset calibration. The input should be set to 0V, and the ADS1242 and ADS1243 compute the OCR value that compensates for offset errors. The Offset Calibration Register (OCR) is updated after this operation. The user must apply a zero input signal to the appropriate analog inputs. The OCR register is automatically updated afterwards. Description: Synchronizes the ADS1242 and ADS1243 to an external event.
PAGE 21
APPLICATION EXAMPLES load cell output can be directly applied to the differential inputs of ADS1242. GENERAL-PURPOSE WEIGHT SCALE HIGH PRECISION WEIGHT SCALE Figure 8 shows a typical schematic of a general-purpose weight scale application using the ADS1242. In this example, the internal PGA is set to either 64 or 128 (depending on the maximum output voltage of the load cell) so that the Figure 9 shows the typical schematic of a high-precision weight scale application using the ADS1242.
PAGE 22
DEFINITION OF TERMS fMOD = An attempt has been made to be consistent with the terminology used in this data sheet. In that regard, the definition of each term is given as follows: PGA SETTING Analog Input Voltage—the voltage at any one analog input relative to GND. Analog Input Differential Voltage—given by the following equation: (IN+) – (IN–).
PAGE 23
Revision History DATE REVISION 10/13 H 2/07 G 12/06 F PAGE SECTION DESCRIPTION 21 Application Examples 10 Overview Changed 1st paragraph of Input Multiplexer subsection. Changed Figure 9; switched plus and minus in upper op amp. 15 Registers Deleted 1xxx from Mux Register definition. 14 Overview Added DSYNC Operation subsection. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. ADS1242, 1243 SBAS235H www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 7-Oct-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 7-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS1242IPWR TSSOP PW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.9 5.6 1.6 8.0 12.0 Q1 ADS1242IPWT TSSOP PW 16 250 180.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 ADS1243IPWR TSSOP PW 20 2500 330.0 16.4 6.95 7.1 1.6 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 7-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1242IPWR TSSOP PW 16 2500 367.0 367.0 35.0 ADS1242IPWT TSSOP PW 16 250 210.0 185.0 35.0 ADS1243IPWR TSSOP PW 20 2500 367.0 367.0 38.0 ADS1243IPWT TSSOP PW 20 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.