Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External VSSOP 10

ADS1244

SBAS273 – DECEMBER 2002

www.ti.com

DESCRIPTION

The ADS1244 is a 24-bit, delta-sigma Analog-to-Digital (A/D)

converter. It offers excellent performance and very low power

in an MSOP-10 package and is well suited for demanding

high-resolution measurements, especially in portable and

other space- and power-constrained systems.

A 3rd-order delta-sigma modulator and digital filter form the

basis of the A/D converter. The analog modulator has a ±5V

differential input range. The digital filter rejects both 50Hz

and 60Hz signals, completely settles in one cycle, and

outputs data at 15 samples per second.

A simple, 2-wire serial interface provides all the necessary

control. Data retrieval, self-calibration, and Sleep Mode are

handled with a few simple waveforms. When only single

conversions are needed, the ADS1244 can be shut down

(Sleep Mode) while idle between measurements to dramati-

cally reduce the overall power dissipation. Multiple ADS1244s

can be connected together to create a synchronously sam-

pling multichannel measurement system. The ADS1244 is

designed to easily connect to microcontrollers, such as the

MSP430.

The ADS1244 supports 2.5V to 5.25V analog supplies and

1.8V to 3.6V digital supplies. Power is typically less than

270µW in normal operation and less than 1µW during Sleep

Mode.

FEATURES

● 20-BIT EFFECTIVE RESOLUTION

● CURRENT CONSUMPTION: 90µA

● ANALOG SUPPLY: 2.5V to 5.25V

● DIGITAL SUPPLY: 1.8V to 3.6V

● ±5V DIFFERENTIAL INPUT RANGE

● 0.0002% INL (TYP), 0.0008% INL (MAX)

● SIMPLE 2-WIRE SERIAL INTERFACE

● SIMULTANEOUS 50Hz AND 60Hz REJECTION

● SINGLE CONVERSIONS WITH SLEEP MODE

● SINGLE-CYCLE SETTLING

● SELF-CALIBRATION

● WELL-SUITED FOR MULTICHANNEL SYSTEMS

● EASILY CONNECTS TO THE MSP430

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Low-Power, 24-Bit

ANALOG-TO-DIGITAL CONVERTER

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

APPLICATIONS

● HAND-HELD INSTRUMENTATION

● PORTABLE MEDICAL EQUIPMENT

● INDUSTRIAL PROCESS CONTROL

● WEIGH SCALES

Digital

Filter

Serial

Interface

DRDY/DOUT

SCLK

CLK

AINN

AINP

VREFP VREFN AVDD

GND

DVDD

3rd-Order

Modulator

Summary of content (24 pages)

PAGE 1
ADS1244 ADS1 244 SBAS273 – DECEMBER 2002 Low-Power, 24-Bit ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● 20-BIT EFFECTIVE RESOLUTION The ADS1244 is a 24-bit, delta-sigma Analog-to-Digital (A/D) converter. It offers excellent performance and very low power in an MSOP-10 package and is well suited for demanding high-resolution measurements, especially in portable and other space- and power-constrained systems. ● CURRENT CONSUMPTION: 90µA ● ANALOG SUPPLY: 2.5V to 5.25V ● DIGITAL SUPPLY: 1.8V to 3.
PAGE 2
ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) AVDD to GND ....................................................................... –0.3V to +6V DVDD to GND ................................................................... –0.3V to +3.6V Input Current ............................................................... 100mA, Momentary Input Current ................................................................ 10mA, Continuous Analog Input Voltage to GND .............................. –0.
PAGE 3
ELECTRICAL CHARACTERISTICS All specifications –40°C to +85°C, AVDD = 5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = 2.5V, unless otherwise specified.
PAGE 4
TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = +5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = +2.5V, unless otherwise specified. ANALOG CURRENT vs TEMPERATURE DIGITAL CURRENT vs TEMPERATURE 110 12 105 10 AVDD = 5V, fCLK = 4.9152MHz 95 Current (µA) Current (µA) 100 90 85 DVDD = 3V, fCLK = 4.9152MHz 8 6 4 80 AVDD = 3V, fCLK = 2.4576MHz 2 75 DVDD = 1.8V, fCLK = 2.
PAGE 5
TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, AVDD = +5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = +2.5V, unless otherwise specified. INTEGRAL NONLINEARITY vs ANALOG SUPPLY INTEGRAL NONLINEARITY vs ANALOG SUPPLY 20 18 VREF = AVDD/2 18 T = –40°C T = 85°C 16 INL (ppm of FSR) 16 INL (ppm of FSR) 20 VREF = AVDD 14 12 10 8 T = 25°C 6 4 14 T = 25°C 12 10 T = –40°C 8 6 4 2 2 T = 85°C 0 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 1.5 2 2.5 3 Analog Supply (V) 4.5 5 5.5 75 95 75 95 1.
PAGE 6
TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, AVDD = +5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = +2.5V, unless otherwise specified.
PAGE 7
OVERVIEW ESD Protection The ADS1244 is an A/D converter comprised of a 3rd-order modulator followed by a digital filter. The modulator measures the differential input signal VIN = (AINP – AINN) against the differential reference VREF = (VREFP – VREFN). Figure 1 shows a conceptual diagram. The differential reference is scaled internally so that the full-scale input range is ±2VREF. The digital filter receives the modulator’s signal and provides a low-noise digital output.
PAGE 8
VOLTAGE REFERENCE INPUTS (VREFP, VREFN) The voltage reference used by the modulator is generated from the voltage difference between VREFP and VREFN: VREF = VREFP – VREFN. The reference inputs use a structure similar to that of the analog inputs. A simplified diagram of the circuitry on the reference inputs is shown in Figure 5. The switches and capacitors can be modeled with an effective  tSAMPLE   / 25pF = 1MΩ for fCLK = 2.4576MHz.
PAGE 9
To help see the response at lower frequencies, Figure 7 illustrates the response out to 180Hz. Notice that both 50Hz and 60Hz signals are rejected. This feature is very useful for eliminating power line cycle interference during measurements. Figure 8 shows the ADS1244’s response around these frequencies. The ADS1244’s data rate and frequency response scale directly with CLK frequency. For example, if fCLK increases from 2.4576MHz to 4.
PAGE 10
POWER-UP Self-calibration is performed at power-up to minimize offset and gain errors. In order for the self-calibration at power-up to work properly, make sure that both AVDD and DVDD increase monotonically and are settled by t1, as shown in Figure 11. SCLK must be held LOW during this time. Once calibration is complete, DRDY/DOUT will go LOW indicating data is ready for retrieval. The time required before the first data is ready (t6) depends on how fast AVDD and DVDD ramp to their final value (t1).
PAGE 11
DATA RETRIEVAL retrieval during the update period. DRDY/DOUT will remain at the state of the last bit shifted out until it is taken HIGH (see t7), indicating that new data is being updated. The ADS1244 continuously converts the analog input signal. To retrieve data, wait until DRDY/DOUT goes LOW, as shown in Figure 12. After this occurs, begin shifting out the data by applying SCLKs. Data is shifted out Most Significant Bit (MSB) first.
PAGE 12
SELF-CALIBRATION When the calibration is complete, DRDY/DOUT will go LOW indicating that new data is ready. There is no need to alter the analog input signal applied to the ADS1244 during calibration, the inputs pins are disconnected within the A/D converter and the appropriate signals applied internally automatically. The first conversion after a calibration is fully settled and valid for use.
PAGE 13
SLEEP MODE Sleep Mode dramatically reduces power consumption (typically < 1µW with CLK stopped) by shutting down all of the active circuitry. To enter Sleep Mode, simply hold SCLK HIGH after DRDY/DOUT goes LOW, as shown in Figure 15. Sleep Mode can be initiated at any time during read back; it is not necessary to retrieve all 24 bits of data beforehand. Once t11 has passed with SCLK held HIGH, Sleep Mode will activate. DRDY/DOUT stays HIGH once Sleep Mode begins. SCLK must remain HIGH to stay in Sleep Mode.
PAGE 14
SINGLE-SUPPLY OPERATION MULTICHANNEL SYSTEMS It is possible to operate the ADS1244 with a single supply. For a 3V supply, simply connect AVDD and DVDD together. Figure 17 shows an example of the ADS1244 running on a single 5V supply. An external resistor, R1, is used to drop 5V supply down to a desired voltage level of DVDD. For example, if the desired DVDD supply voltage is 3V and AVDD is 5V, the value of R1 should be: Multiple ADS1244s can be operated in parallel to measure multiple input signals.
PAGE 15
WEIGH SCALE SYSTEM differential gain stage noise and reduce mechanical vibration noise from the load cell. The cutoff frequency of the low-pass filter should be as low as possible to minimize the overall system noise. The reference voltage is typically generated by dividing down the supply voltage (RVR1, RVR2). Use a bypass capacitor located as close to VREFP as possible. Figure 19 shows an example of a weigh scale system.
PAGE 16
SUMMARY OF SERIAL INTERFACE WAVEFORMS DRDY/DOUT 23 22 21 0 MSB SCLK LSB 1 24 a. Data Retrieval. DRDY/DOUT 23 SCLK 22 21 0 1 24 25 b. Data Retrieval with DRDY/DOUT Forced HIGH Afterwards. Data ready after cal. DRDY/DOUT 23 22 21 0 Begin cal. SCLK 1 24 25 26 c. Self-Calibration. Data ready. Sleep Mode 23 DRDY/DOUT 22 21 0 Wakeup and start conversion. SCLK 1 24 d. Sleep Mode/Single Conversions. Data ready after wakeup and cal.
PAGE 17
PACKAGE DRAWING DGS (S-PDSO-G10) PLASTIC SMALL-OUTLINE PACKAGE 0,27 0,17 0,50 10 0,08 M 6 0,15 NOM 3,05 2,95 4,98 4,78 Gage Plane 0,25 1 0°– 6° 5 3,05 2,95 0,69 0,41 Seating Plane 1,07 MAX 0,15 0,05 0,10 4073272/B 08/01 NOTES: A. B. C. A. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-187 ADS1244 SBAS273 www.ti.
PAGE 18
PACKAGE OPTION ADDENDUM www.ti.
PAGE 19
PACKAGE OPTION ADDENDUM www.ti.
PAGE 20
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS1244IDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS1244IDGST VSSOP DGS 10 250 180.0 12.4 5.3 3.4 1.4 8.0 12.
PAGE 21
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1244IDGSR VSSOP DGS 10 2500 367.0 367.0 35.0 ADS1244IDGST VSSOP DGS 10 250 210.0 185.0 35.
PAGE 22
PAGE 23
PAGE 24
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.