Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External VSSOP 10

FEATURES

D 20-Bit Effective Resolution

D High-Impedance Buffered Input

D ±2.5V Differential Input Range

D Pin-Compatible with ADS1244

D 0.0006% INL (typ), 0.0015% INL (max)

D Simple Two-Wire Serial Interface

D Simultaneous 50Hz and 60Hz Rejection

D Single Conversions with Sleep Mode

D Single-Cycle Settling

D Self-Calibration

D Well Suited for Multi-Channel Systems

D Easily Connects to the MSP430

D Current Consumption: 158µA

D Analog Supply: 2.5V to 5.25V

D Digital Supply: 1.8V to 3.6V

APPLICATIONS

D Hand-Held Instrumentation

D Portable Medical Equipment

D Industrial Process Control

D Test and Measurement Systems

DESCRIPTION

The ADS1245 is a 24-bit, delta-sigma analog-to-digital

converter (ADC). It offers excellent performance and very

low power in an MSOP-10 package and is well suited for

demanding high-resolution measurements, especially in

portable and other space- and power-constrained

systems.

The buffered input presents an impedance of 3GΩ, mini-

mizing measurement errors when using high-impedance

sources. The ADS1245 is compatible with ADS1244 and

offers a direct upgrade path for designs requiring higher in-

put impedance.

A third-order delta-sigma (∆Σ) modulator and digital filter

form the basis of the ADC. The analog modulator has a

±2.5V differential input range. The digital filter rejects both

50Hz and 60Hz signals, completely settles in one cycle,

and outputs data at 15 samples per second (SPS).

A simple, two-wire serial interface provides all the

necessary control. Data retrieval, self-calibration, and

Sleep mode are handled with a few simple waveforms.

When only single conversions are needed, the ADS1245

can be shut down (Sleep mode) while idle between

measurements to dramatically reduce the overall power

dissipation. Multiple ADS1245s can be connected

together to create a synchronously sampling multichannel

measurement system. The ADS1245 is designed to easily

connect to microcontrollers, such as the MSP430.

The ADS1245 supports 2.5V to 5.25V analog supplies and

1.8V to 3.6V digital supplies. Power is typically less than

470µW in normal operation and less than 1µW during

Sleep mode.

Digital

Filter

Serial

Interface

DRDY/DOUT

SCLK

CLK

AINN

AINP

VREFP VREFN AVDD

GND

DVDD

3rd−Order

Modulator

Buffer

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SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003

Low-Power, 24-Bit

Analog-to-Digital Converter

ADS1245

www.ti.com

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (22 pages)

PAGE 1
ADS1245 SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 Low-Power, 24-Bit Analog-to-Digital Converter FEATURES DESCRIPTION D D D D D D D D D D D D D D D The ADS1245 is a 24-bit, delta-sigma analog-to-digital converter (ADC). It offers excellent performance and very low power in an MSOP-10 package and is well suited for demanding high-resolution measurements, especially in portable and other space- and power-constrained systems. 20-Bit Effective Resolution High-Impedance Buffered Input ±2.
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"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 ORDERING INFORMATION PRODUCT PACKAGE−LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ADS1245 MSOP-10 DGS −40°C to +85°C BHI ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS1245IDGST Tape and Reel, 250 ADS1245IDGSR Tape and Reel, 2500 (1) For the most current specifications and package information, refer to our web site at www.ti.com.
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"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 ELECTRICAL CHARACTERISTICS All specifications at TA = −40°C to +85°C, AVDD = +5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = +1.25V, unless otherwise noted.
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"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = +5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = +1.25V, unless otherwise specified. ANALOG CURRENT vs TEMPERATURE DIGITAL CURRENT vs TEMPERATURE 220 12 210 200 10 DVDD = +3V, fCLK = 4.9152MHz 180 AVDD = +5V, fCLK = 4.9152MHz Current (µA) Current (µA) 190 170 160 150 6 4 AVDD = +3V, fCLK = 2.4576MHz 140 8 130 2 120 110 100 DVDD = +1.8V, fCLK = 2.
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"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = +5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = +1.25V, unless otherwise specified. GAIN vs TEMPERATURE 1.00006 4 1.00005 3 1.00004 2 Gain (Normalized) Normalized Offset (ppm of FSR) OFFSET vs TEMPERATURE 5 1 0 −1 −2 1.00002 1.00001 1.00000 0.99999 0.99998 0.99997 −3 0.99996 −4 −5 1.00003 −45 −25 −5 15 35 55 75 95 0.99995 0.
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"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = +5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = +1.25V, unless otherwise specified.
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"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 OVERVIEW The ADS1245 is an ADC comprised of a 3rd-order modulator followed by a digital filter. The modulator measures the differential input signal VIN = (AINP – AINN) against the differential reference VREF = (VREFP – VREFN). Figure 15 shows a conceptual diagram. The differential reference is scaled internally so that the full-scale input range is ±2VREF.
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"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 For best performance, bypass the voltage reference inputs with a 0.1µF capacitor between VREFP and VREFN. Place the capacitor as close as possible to the pins. ESD diodes protect the inputs. To keep these diodes from turning on, make sure the voltages on the input pins do not go below GND by more than 100mV, and likewise do not exceed AVDD by 100mV. CLOCK INPUT (CLK) This digital input supplies the system clock to the ADS1245.
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"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 To help see the response at lower frequencies, Figure 19 illustrates the response out to 180Hz. Notice that both 50Hz and 60Hz signals are rejected. This feature is very useful for eliminating power line cycle interference during measurements. Figure 20 shows the ADS1245 response around these frequencies. SETTLING TIME 0 −60 The ADS1245 has single-cycle settling.
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"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 Begin New Conversion, Previous Conversion Data New Conversion Complete Complete Previous Conversion DRDY/DOUT tDELAY VIN Figure 22. Analog Input Change Timing POWER−UP Self-calibration is performed at power-up to minimize offset and gain errors. In order for the self-calibration at power-up to work properly, make sure that both AVDD and DVDD increase monotonically and are settled by t1, as shown in Figure 23.
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"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 DATA FORMAT DATA RETRIEVAL The ADS1245 outputs 24 bits of data in Binary Two’s Complement format. The least significant bit (LSB) has a weight of (2VREF)/(223 − 1). A positive full-scale input produces an output code of 7FFFFFh and the negative full-scale input produces an output code of 8000000h. The output clips at these codes for signals exceeding full-scale. Table 1 summarizes the ideal output codes for different input signals.
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"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 Data Data is ready. New data is ready. DRDY/DOUT 23 22 21 0 1 SCLK 24 25 25th SCLK to force DRDY/DOUT high Figure 25. Data Retrieval with DRDY/DOUT Forced High Afterwards SELF-CALIBRATION When the calibration is complete, DRDY/DOUT will go low, indicating that new data is ready.
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"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 SLEEP MODE Sleep Mode with Self-Calibration Sleep mode dramatically reduces power consumption (typically < 1µW with CLK stopped) by shutting down all of the active circuitry. To enter Sleep mode, simply hold SCLK high after DRDY/DOUT goes low, as shown in Figure 27. Sleep Mode can be initiated at any time during read-back; it is not necessary to retrieve all 24 bits of data beforehand.
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"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 SINGLE CONVERSIONS When only single conversions are needed, Sleep mode can be used to start and stop the ADS1245. To make a single conversion, first enter the Sleep Mode holding SCLK high. Now, when ready to start the conversion, take SCLK low. The ADS1245 will wake up and begin the conversion. Wait for DRDY/DOUT to go low, and then retrieve the data. Afterwards, take SCLK high to stop the ADS1245 from converting and re−enter Sleep mode.
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"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 ADS1245 1 GND CLK 10 2 VREFP SCLK 9 3 VREFN DRDY/DOUT 8 4 AINN DVDD 7 5 AINP AVDD 6 OUT1 IN1 ADS1245 1 GND CLK 10 2 VREFP SCLK 9 3 VREFN DRDY/DOUT 8 4 AINN DVDD 7 5 AINP AVDD 6 OUT2 IN2 CLK and SCLK Sources OUT1 t14 OUT2 SYMBOL DESCRIPTION t14 Difference between DRDY/ DOUTs going low in multichannel systems. MIN MAX UNITS ± 500 µs Figure 30.
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"#$%& www.ti.com SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 SUMMARY OF SERIAL INTERFACE WAVEFORMS DRDY/DOUT 23 22 21 0 MSB LSB 1 SCLK 24 a. Data Retrieval DRDY/DOUT 23 SCLK 22 21 0 1 24 25 b. Data Retrieval with DRDY/DOUT Forced High Afterwards Data ready after calibration DRDY/DOUT 23 22 21 0 Begin calibration SCLK 1 24 25 26 c. Self-Calibration Data ready Sleep Mode 23 DRDY/DOUT 22 21 0 Wakeup and start conversion SCLK 1 24 d.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS1245IDGST Package Package Pins Type Drawing VSSOP DGS 10 SPQ 250 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 180.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 3.4 1.4 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1245IDGST VSSOP DGS 10 250 210.0 185.0 35.
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