ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com 24-Bit Analog-to-Digital Converters for Temperature Sensors Check for Samples: ADS1246, ADS1247, ADS1248 FEATURES DESCRIPTION • • • • • • • • • The ADS1246, ADS1247, and ADS1248 are highly-integrated, precision, 24-bit analog-to-digital converters (ADCs).
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS Minimum/maximum specifications apply from –40°C to +105°C. Typical specifications are at +25°C. All specifications at AVDD = +5V, DVDD = +3.3V, AVSS = 0V, VREF = +2.048V, and oscillator frequency = 4.096MHz, unless otherwise noted. ADS1246, ADS1247, ADS1248 PARAMETER CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Full-scale input voltage (VIN = ADCINP – ADCINN) ±VREF/PGA (1) (VIN)(Gain) AVSS + 0.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum/maximum specifications apply from –40°C to +105°C. Typical specifications are at +25°C. All specifications at AVDD = +5V, DVDD = +3.3V, AVSS = 0V, VREF = +2.048V, and oscillator frequency = 4.096MHz, unless otherwise noted.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com THERMAL INFORMATION ADS1246, ADS1247, ADS1248 THERMAL METRIC (1) UNITS TSSOP (IPW) 28 θJA Junction-to-ambient thermal resistance (2) θJC(top) Junction-to-case(top) thermal resistance 54.6 (3) 11.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com ADS1248 (TSSOP-28) PIN DESCRIPTIONS NAME PIN NO. FUNCTION DVDD 1 Digital Digital power supply DESCRIPTION DGND 2 Digital Digital ground CLK 3 Digital input External clock input. Tie this pin to DGND to activate the internal oscillator. RESET 4 Digital input Chip reset (active low). Returns all register values to reset values.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com PW PACKAGE TSSOP-20 (TOP VIEW) DVDD 1 20 SCLK DGND 2 19 DIN CLK 3 18 DOUT/DRDY RESET 4 17 DRDY REFP0/GPIO0 5 16 CS ADS1247 REFN0/GPIO1 6 15 START VREFOUT 7 14 AVDD VREFCOM 8 13 AVSS AIN0/IEXC 9 12 AIN3/IEXC/GPIO3 AIN1/IEXC 10 11 AIN2/IEXC/GPIO2 ADS1247 (TSSOP-20) PIN DESCRIPTIONS NAME PIN NO.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com PW PACKAGE TSSOP-16 (TOP VIEW) DVDD 1 16 SCLK DGND 2 15 DIN CLK 3 14 DOUT/DRDY RESET 4 13 DRDY ADS1246 REFP 5 12 CS REFN 6 11 START AINP 7 10 AVDD AINN 8 9 AVSS ADS1246 (TSSOP-16) PIN DESCRIPTIONS NAME PIN NO. FUNCTION DVDD 1 Digital Digital power supply DESCRIPTION DGND 2 Digital Digital ground CLK 3 Digital input External clock input.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com TIMING DIAGRAMS tCSPW CS tCSSC tSPWH tSCLK tSCCS SCLK DIN DIN[0] tSPWL tDIHD tDIST DIN[7] DIN[6] DIN[5] DOUT[7] DOUT[6] DOUT[5] DIN[4] DIN[1] tDOPD DOUT/DRDY (1) DIN[0] tDOHD DOUT[4] DOUT[1] DOUT[0] tCSDO Figure 1. Serial Interface Timing Timing Characteristics for Figure 1 (1) At TA = -40°C to +105°C and DVDD = 2.7V to 5.5V.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com tSTART START Figure 3. Minimum START Pulse Width Timing Characteristics for Figure 3 At TA = -40°C to +105°C and DVDD = 2.7V to 5.5V. SYMBOL tSTART DESCRIPTION MIN START pulse width high MAX 3 UNIT tOSC tRESET RESET CS SCLK tRHSC Figure 4. Reset Pulse Width and SPI Communication After Reset Timing Characteristics for Figure 4 At TA = -40°C to +105°C and DVDD = 2.7V to 5.5V.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com NOISE PERFORMANCE The ADS1246/7/8 noise performance can be optimized by adjusting the data rate and PGA setting. As the averaging is increased by reducing the data rate, the noise drops correspondingly. Increasing the PGA value reduces the input-referred noise, particularly useful when measuring low-level signals. Table 1 to Table 6 summarize noise performance of the ADS1246/7/8.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com Table 3. Noise in μVRMS and (μVPP) at AVDD = 5V, AVSS = 0V, and Internal Reference = 2.048V DATA RATE (SPS) PGA SETTING 1 2 4 8 16 32 64 128 5 1.35 (7.78) 0.7 (4.17) 0.35 (2.03) 0.17 (0.95) 0.1 (0.53) 0.06 (0.32) 0.05 (0.31) 0.05 (0.29) 10 1.8 (10.82) 0.88 (5.26) 0.5 (2.75) 0.24 (1.47) 0.13 (0.8) 0.09 (0.49) 0.07 (0.39) 0.07 (0.4) 20 2.62 (14.32) 1.22 (7.05) 0.66 (3.88) 0.35 (2.05) 0.19 (1.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com Table 5. Noise in μVRMS and (μVPP) at AVDD = 3V, AVSS = 0V, and Internal Reference = 2.048V DATA RATE (SPS) PGA SETTING 1 2 4 8 16 32 64 128 5 2.5 (14.24) 1.32 (6.92) 0.67 (3.48) 0.32 (1.68) 0.17 (0.9) 0.09 (0.51) 0.08 (0.42) 0.07 (0.39) 10 3.09 (16.85) 1.69 (9.32) 0.82 (4.68) 0.42 (2.41) 0.23 (1.18) 0.11 (0.63) 0.11 (0.66) 0.1 (0.55) 20 4.55 (24.74) 2.19 (12.82) 1.07 (5.94) 0.55 (3.38) 0.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted. OFFSET vs TEMPERATURE OFFSET vs TEMPERATURE 10 8 AVDD = 3.3V Data Rate = 640SPS 6 PGA = 1 4 PGA = 32 2 0 -2 AVDD = 3.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted. GAIN vs TEMPERATURE GAIN vs TEMPERATURE 0.04 0.04 AVDD = 3.3V Data Rate = 20SPS 0.03 AVDD = 3.3V Data Rate = 160SPS 0.03 PGA = 128 0.02 PGA = 32 Gain Error (%) Gain Error (%) 0.02 0.01 0 PGA = 1 -0.01 PGA = 128 0.01 -0.01 -0.02 -0.02 -0.03 -0.03 -0.04 PGA = 1 0 PGA = 32 -0.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted. INTEGRAL NONLINEARITY vs INPUT SIGNAL INTEGRAL NONLINEARITY vs INPUT SIGNAL 8 8 +105°C -40°C PGA = 128 Data Rate = 20SPS 6 6 -10°C 4 -40°C INL (ppm of FSR) INL (ppm of FSR) 4 -10°C 2 0 -2 +25°C -4 +25°C 2 0 -2 -4 +105°C -6 PGA = 1 Data Rate = 2kSPS -6 -8 -100 0 -50 50 -8 -100 100 Figure 35.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted. IDAC DRIFT POWER-SUPPLY REJECTION vs GAIN 0.004 8 1.5mA Setting, 10 Units Power-Supply Rejection (mV/V) IEXC1 - IEXC2 (mA) 0.003 0.002 0.001 0 -0.001 -0.002 -0.003 -0.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted. IDAC VOLTAGE COMPLIANCE IDAC VOLTAGE COMPLIANCE 1.01 1.1 1.005 Normalized IDAC Current Normalized IDAC Current 1 0.9 0.8 0.7 0.6 0.5 50µA 100µA 250µA 500µA 750µA 1mA 1.5mA 0.4 0.3 0.2 0.1 0 0 1 1 0.995 0.99 0.985 2 3 Voltage (V) 4 5 0.98 0 1 Figure 47.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com GENERAL DESCRIPTION OVERVIEW The ADS1247 and ADS1248 also include a flexible input multiplexer with system monitoring capability and general-purpose I/O settings, a very low-drift voltage reference, and two matched current sources for sensor excitation. Figure 49 and Figure 50 show the various functions incorporated in each device. The ADS1246, ADS1247 and ADS1248 are highly integrated 24-bit data converters.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com ADC INPUT AND MULTIPLEXER The ADS1246/7/8 ADC measures the input signal through the onboard PGA. All analog inputs are connected to the internal AINP or AINN analog inputs through the analog multiplexer. A block diagram of the analog input multiplexer is shown in Figure 51.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com ESD diodes protect the ADC inputs. To prevent these diodes from turning on, make sure the voltages on the input pins do not go below AVSS by more than 100mV, and do not exceed AVDD by more than 100mV, as shown in Equation 2. Note that the same caution is true if the inputs are configured to be GPIOs.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com LOW-NOISE PGA MODULATOR The ADS1246/7/8 feature a low-drift, low-noise, high input impedance programmable gain amplifier (PGA). The PGA can be set to gain of 1, 2, 4, 8, 16, 32, 64, or 128 by register SYS0. A simplified diagram of the PGA is shown in Figure 53. A third-order modulator is used in the ADS1246/7/8. The modulator converts the analog input voltage into a pulse code modulated (PCM) data stream.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 0 -60 -20 -70 Magnitude (dB) Magnitude (dB) www.ti.com -40 -60 -80 -80 -90 -100 -110 -100 -120 -120 0 20 40 60 80 48 100 120 140 160 180 200 50 Figure 54. Filter Profile with Data Rate = 5SPS 52 54 56 58 60 62 Frequency (Hz) Frequency (Hz) Figure 57.
ADS1246 ADS1247 ADS1248 www.ti.com 0 0 -20 -20 Magnitude (dB) Magnitude (dB) SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 -40 -60 -80 -100 -40 -60 -80 -100 -120 -120 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 1 2 3 Frequency (Hz) 0 0 -20 -20 -40 -60 -80 -100 6 7 8 9 10 -40 -60 -80 -100 -120 -120 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 0 2 4 Frequency (Hz) Figure 61.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com INTERNAL VOLTAGE REFERENCE The ADS1247/8 includes an onboard voltage reference with a low temperature coefficient. The output of the voltage reference is 2.048V with the capability of both sourcing and sinking up to 10mA of current. The voltage reference must have a capacitor connected between VREFOUT and VREFCOM. The value of the capacitance should be in the range of 1μF to 47μF.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com GENERAL-PURPOSE DIGITAL I/O Power-Supply Monitor The ADS1248 has eight pins and the ADS1247 has four pins that serve a dual purpose as either analog inputs or general-purpose digital inputs/outputs (GPIOs). The system monitor can measure the analog or digital power supply. When measuring the power supply, the resulting conversion is approximately 1/4 of the actual power supply voltage.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com CALIBRATION Offset Calibration Register: OFC[2:0] The conversion data are scaled by offset and gain registers before yielding the final output code. As shown in Figure 66, the output of the digital filter is first subtracted by the offset register (OSC) and then multiplied by the full-scale register (FSC). A digital clipping circuit ensures that the output code does not exceed 24 bits. Equation 7 shows the scaling.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 Calibration Commands The ADS1246/7/8 provide commands for three types of calibration: system gain calibration, system offset calibration and self offset calibration. Where absolute accuracy is needed, it is recommended that calibration be performed after power on, a change in temperature, a change of PGA and in some cases a change in channel.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com ADC CONTROL ADC Conversion Control The START pin provides easy and precise control of conversions. Pulse the START pin high to begin a conversion, as shown in Figure 67 and Table 15. The conversion completion is indicated by the DOUT/DRDY pin going low. When the conversion completes, the ADS1246/7/8 automatically shuts down to save power.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 With the START pin held high, the ADC converts the selected input channels continuously. This configuration continues until the START pin is taken low. The START pin can also be used to perform the synchronized measurement for the multi-channel applications by pulsing the START pin. When the RESET pin goes low, the device is immediately reset. All the registers are restored to default values.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com Table 16. Data Conversion Time FIRST DATA CONVERSION TIME AFTER FILTER RESET SYNC COMMAND, MUX0 REGISTER WRITE NOMINAL DATA RATE (SPS) (1) EXACT DATA RATE (SPS) (ms) (1) NO. OF SYSTEM CLOCK CYCLES HARDWARE RESET, RESET COMMAND, START PIN HIGH, WAKEUP COMMAND, VBIAS, MUX1, or SYS0 REGISTER WRITE SECOND AND SUBSEQUENT CONVERSION TIME AFTER FILTER RESET (ms) (1) NO. OF SYSTEM CLOCK CYCLES (ms) NO.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com SCLK The serial clock signal. SCLK provides the clock for serial communication. It is a Schmitt-trigger input, but it is highly recommended that SCLK be kept as clean as possible to prevent glitches from inadvertently shifting the data. Data are shifted into DIN on the falling edge of SCLK and shifted out of DOUT on the rising edge of SCLK. DIN The data input pin. DIN is used along with SCLK to send data to the device.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com SCLK DOUT/DRDY(1) 1 2 3 22 D[23] D[22] D[21] D[2] 23 D[1] 24 D[0] 1 2 D[23] D[22] NOP DIN 24 D[0] NOP DRDY (1) CS tied low. Figure 70. Data Retrieval with the DRDY MODE Bit = 1 (Enabled) SCLK DOUT/DRDY(1) DIN 1 2 3 22 D[23] D[22] D[21] D[2] 23 D[1] 24 1 2 8 D[0] NOP 1 2 D[23] D[22] NOP 24 D[0] NOP DRDY (1) DRDY MODE bit enabled, CS tied low. Figure 71.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com REGISTER DESCRIPTIONS ADS1246 REGISTER MAP Table 18.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com ADS1246 DETAILED REGISTER DEFINITIONS (continued) VBIAS—Bias Voltage Register. This register enables a bias voltage on the analog inputs. VBIAS - ADDRESS 01h RESET VALUE = 00h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 0 0 0 0 VBIAS1 VBIAS0 Bits 7:2 These bits must always be set to '000000'.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com ADS1246 DETAILED REGISTER DEFINITIONS (continued) SYS0—System Control Register 0. SYS0 - ADDRESS 03h RESET VALUE = 00h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 PGA2 PGA1 PGA0 DOR3 DOR2 DOR1 DOR0 Bit 7 These bits must always be set to '0'. Bits 6:4 PGA2:0 These bits determine the gain of the PGA.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com ADS1246 DETAILED REGISTER DEFINITIONS (continued) FSC23:0 These bits make up the full-scale calibration coefficient register. FSC0—Full-Scale Calibration Coefficient Register 0 RESET VALUE IS PGA DEPENDENT (1) FSC0 - ADDRESS 07h (1) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0 The reset value for FSC is factory-trimmed for each PGA setting.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com ADS1247 AND ADS1248 REGISTER MAP Table 20.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com ADS1247 and ADS1248 DETAILED REGISTER DEFINITIONS MUX0—Multiplexer Control Register 0. This register allows any combination of differential inputs to be selected on any of the input channels. Note that this setting can be superceded by the MUXCAL and VBIAS bits.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com ADS1247 and ADS1248 DETAILED REGISTER DEFINITIONS (continued) MUX1—Multiplexer Control Register 1 MUX1 - ADDRESS 02h RESET VALUE = 00h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CLKSTAT VREFCON1 VREFCON0 REFSELT1 REFSELT0 MUXCAL2 MUXCAL1 MUXCAL0 Bit 7 CLKSTAT This bit is read-only and indicates whether the internal or external oscillator is being used.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com ADS1247 and ADS1248 DETAILED REGISTER DEFINITIONS (continued) SYS0—System Control Register 0 SYS0 - ADDRESS 03h RESET VALUE = 00h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 PGA2 PGA1 PGA0 DOR3 DOR2 DOR1 DOR0 Bit 7 This bit must always be set to '0' Bits 6:4 PGA2:0 These bits determine the gain of the PGA.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com ADS1247 and ADS1248 DETAILED REGISTER DEFINITIONS (continued) FSC23:0 These bits make up the full-scale calibration coefficient register. FSC0—Full-Scale Calibration Coefficient Register 0 RESET VALUE IS PGA DEPENDENT (1) FSC0 - ADDRESS 07h (1) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0 The reset value for FSC is factory-trimmed for each PGA setting.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com ADS1247 and ADS1248 DETAILED REGISTER DEFINITIONS (continued) GPIOCFG—GPIO Configuration Register.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com SPI COMMANDS SPI COMMAND DEFINITIONS The commands shown in Table 22 control the operation of the ADS1246/7/8. Some of the commands are stand-alone commands (for example, RESET), whereas others require additional bytes (for example, WREG requires command, count, and the data bytes). Operands: n = number of registers to be read or written (number of bytes – 1) r = register (0 to 15) x = don't care Table 22.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com SYSTEM CONTROL COMMANDS WAKEUP—Wake up from sleep mode that is set by the SLEEP command. Use this command to awaken the device from sleep mode. After execution of the WAKEUP command, the device wakes up on the rising edge of the eighth SCLK. SLEEP—Set the device to sleep mode; can only be awakened by the WAKEUP command. This command places the part into a sleep (power-saving) mode.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com DATA RETRIEVAL COMMANDS RDATAC—Read data continuously. The RDATAC command enables the automatic loading of a new conversion result into the output data register. In this mode, the conversion result can be received once from the device after the DRDY signal goes low by sending 24 SCLKs. It is not necessary to read back all the bits, as long as the number of bits read out is a multiple of eight.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com RDATA—Read data once. The RDATA command loads the most recent conversion result into the output register. After issuing this command, the conversion result can be read out by sending 24 SCLKs, as shown in Figure 78. This command also works in RDATAC mode.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com USER REGISTER READ AND WRITE COMMANDS RREG—Read from registers. This command outputs the data from up to 16 registers, starting with the register address specified as part of the instruction. The number of registers read is one plus the second byte. If the count exceeds the remaining registers, the addresses wrap back to the beginning. First Command Byte: 0010 rrrr, where rrrr is the address of the first register to read.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com CALIBRATION COMMANDS The ADS1246/7/8 provide system and offset calibration commands and a system gain calibration command. SYSOCAL—Offset system calibration. This command initiates a system offset calibration. For a system offset calibration, the input should be externally set to zero. The OFC register is updated when this operation completes. SYSGCAL—System gain calibration.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com APPLICATION INFORMATION SPI COMMUNICATION EXAMPLES negative terminal of both sensors (that is, channels AIN1 and AIN3). All these settings can be changed by performing a block write operation on the first four registers of the device. After the DRDY pin goes low, the conversion result can be immediately retrieved by sending in 16 SPI clock pulses because the device defaults to RDATAC mode.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com Sleep Mode Example This second example deals with performing one conversion after power-up and then entering into the power-saving sleep mode. In this example, a sensor is connected to input channels AIN0 and AIN1. Commands to set up the devices must occur at least 216 system clock cycles after powering up the devices. The ADC operates at a data rate of 2kSPS. The PGA gain is set to 32 for both sensors.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com Hardware-Compensated, Three-Wire RTD Measurement Example be equal to the resistance of the PT-100 sensor at +25°C (approximately 110Ω). The IDAC current is set to 1.5mA. This setting results in a differential input swing of ±14.7mV at the inputs of the ADC. The PGA gain is set to 128. The full-scale input for the ADC is ±19.53mV. Fixing RBIAS at 833Ω fixes the reference at 2.5V and the input common-mode at approximately 2.
ADS1246 ADS1247 ADS1248 SBAS426G – AUGUST 2008 – REVISED OCTOBER 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (June 2011) to Revision G Page • Added Figure 46 ................................................................................................................................................................. 21 • Added Figure 47 and Figure 48 ..........................................
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 5.6 1.6 8.0 12.0 Q1 ADS1246IPWR TSSOP PW 16 2000 330.0 12.4 6.9 ADS1247IPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 ADS1248IPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1246IPWR TSSOP PW 16 2000 367.0 367.0 35.0 ADS1247IPWR TSSOP PW 20 2000 367.0 367.0 38.0 ADS1248IPWR TSSOP PW 28 2000 367.0 367.0 38.
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