Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External SSOP 20

24-Bit, 20kHz, Low Power

ANALOG-TO-DIGITAL CONVERTER

FEATURES

● 24 BITS—NO MISSING CODES

● 19 BITS EFFECTIVE RESOLUTION UP TO

20kHz DATA RATE

● LOW NOISE: 1.8ppm

● FOUR DIFFERENTIAL INPUTS

● INL: 15ppm (max)

● EXTERNAL REFERENCE (0.5V to 5V)

● POWER-DOWN MODE

● SYNC MODE

● LOW POWER: 4mW at 20kHz

● SEPARATE DIGITAL INTERFACE SUPPLY 1.8V

to 3.6V

DESCRIPTION

The ADS1254 is a precision, wide dynamic range, delta-

sigma, Analog-to-Digital (A/D) converter with 24-bit resolu-

tion. The delta-sigma architecture is used for wide dynamic

range and to ensure 24 bits of no missing codes perfor-

mance. An effective resolution of 19 bits (1.8ppm of rms

noise) is achieved for conversion rates up to 20kHz.

The ADS1254 is designed for high-resolution measurement

applications in cardiac diagnostics, smart transmitters, indus-

trial process control, weight scales, chromatography, and

portable instrumentation. The converter includes a flexible,

two-wire synchronous serial interface for low-cost isolation.

The ADS1254 is a multi-channel converter and is offered in

an SSOP-20 package.

APPLICATIONS

● CARDIAC DIAGNOSTICS

● DIRECT THERMOCOUPLE INTERFACES

● BLOOD ANALYSIS

● INFRARED PYROMETERS

● LIQUID/GAS CHROMATOGRAPHY

● PRECISION PROCESS CONTROL

ADS1254

SBAS213B – JUNE 2001 – REVISED JUNE 2006

4th-Order

∆Σ

Modulator

Digital

Filter

Serial

Interface

Control

CLK

REF

SCLK

DOUT/DRDY

AGND

DGND

ADS1254

Mux

CH1+

CH1–

CH2+

CH2–

CH3+

CH3–

CH4+

CH4–

CHSEL0

CHSEL1

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

ADS1254

All trademarks are the property of their respective owners.

Summary of content (23 pages)

PAGE 1
ADS1254 ADS 125 4 SBAS213B – JUNE 2001 – REVISED JUNE 2006 24-Bit, 20kHz, Low Power ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● 24 BITS—NO MISSING CODES ● 19 BITS EFFECTIVE RESOLUTION UP TO 20kHz DATA RATE ● LOW NOISE: 1.8ppm ● FOUR DIFFERENTIAL INPUTS ● INL: 15ppm (max) ● EXTERNAL REFERENCE (0.5V to 5V) ● POWER-DOWN MODE ● SYNC MODE ● LOW POWER: 4mW at 20kHz ● SEPARATE DIGITAL INTERFACE SUPPLY 1.8V to 3.
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ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) Analog Input: Current (Momentary) .............................................. ±100mA (Continuous) ............................................... ±10mA Voltage ................................... GND – 0.3V to VDD + 0.3V AVDD to AGND ....................................................................... –0.3V to 6V DVDD to AVDD .......................................................................... –6V to +6V DVDD to DGND ..............
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ELECTRICAL CHARACTERISTICS All specifications at TMIN to TMAX, AVDD = +5V, DVDD = +1.8V. CLK = 8MHz, and VREF = 4.096, unless otherwise specified.
PAGE 4
TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = +5V, DVDD = +1.8V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified. EFFECTIVE RESOLUTION vs DATA OUTPUT RATE 20.0 1.9 19.8 1.8 19.6 Effective Resolution (Bits) RMS Noise (ppm of FS) RMS NOISE vs DATA OUTPUT RATE 2.0 1.7 1.6 1.5 1.4 1.3 1.2 1.1 19.4 19.2 19.0 18.8 18.6 18.4 18.2 1.0 100 1k 10k 18.0 100k 100 1k Data Ouput Rate (Hz) 20.0 1.8 19.8 1.6 19.6 Effective Resolution (Bits) RMS Noise (ppm of FS) 2.0 1.4 1.2 1.0 0.8 0.
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TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, AVDD = +5V, DVDD = +1.8V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified. INTEGRAL NONLINEARITY vs TEMPERATURE RMS NOISE vs INPUT VOLTAGE 2.5 2.0 RMS Noise (ppm of FS) 2.0 INL (ppm of FS) 1.5 1.0 0.5 1.5 1.0 0.
PAGE 6
TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, AVDD = +5V, DVDD = +1.8V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified. CMR vs COMMON-MODE FREQUENCY CMR AT 60Hz vs CLK FREQUENCY –70 –50 –75 –80 CMR (dB) CMR at 60Hz (dB) –60 –70 –80 –85 –90 –90 –95 –100 –100 –110 –105 0 1 2 3 4 5 6 7 8 10 100 0.8 4.0 0.7 3.5 0.6 AVDD (5V) DVDD (1.8V) 0.4 0.3 0.2 0.1 3.0 Analog (5V) Digital (3.3V) Digital (1.8V) 2.5 2.0 1.5 1.
PAGE 7
THEORY OF OPERATION The ADS1254 is a precision, high-dynamic range, 24-bit, delta-sigma, A/D converter capable of achieving very high-resolution digital results at high data rates. The analog-input signal is sampled at a rate determined by the frequency of the system clock (CLK). The sampled analog input is modulated by the delta-sigma A/D modulator, which is followed by a digital filter.
PAGE 8
DELTA-SIGMA MODULATOR REFERENCE INPUT The ADS1254 operates from a nominal system clock frequency of 8MHz. The modulator frequency is fixed in relation to the system clock frequency. The system clock frequency is divided by 6 to derive the modulator frequency. Therefore, with a system clock frequency of 8MHz, the modulator frequency is 1.333MHz. Furthermore, the oversampling ratio of the modulator is fixed in relation to the modulator frequency.
PAGE 9
DIGITAL FILTER RESPONSE 0 –20 –20 –40 –40 –60 –60 –80 –80 Gain (dB) Gain (dB) NORMALIZED DIGITAL FILTER RESPONSE 0 –100 –120 –100 –120 –140 –140 –160 –160 –180 –180 –200 –200 0 1 2 3 4 5 6 7 8 9 0 10 50 100 FIGURE 4. Normalized Digital Filter Response. 250 300 DIGITAL FILTER RESPONSE 0 0 –20 –20 –40 –40 –60 –60 –80 Gain (dB) Gain (dB) 200 FIGURE 5. Digital Filter Response (50Hz).
PAGE 10
DIGITAL FILTER RESPONSE 0 –20 –20 –40 –40 –60 –60 –80 –80 Gain (dB) Gain (dB) DIGITAL FILTER RESPONSE 0 –100 –120 –100 –120 –140 –140 –160 –160 –180 –180 –200 –200 55 56 57 58 59 60 61 62 63 64 55 65 56 57 58 59 60 61 62 63 64 65 Frequency (Hz) Frequency (Hz) FIGURE 10. Expanded Digital Filter Response (60Hz with a 60Hz Data Output Rate). FIGURE 11. Expanded Digital Filter Response (60Hz with a 10Hz Data Output Rate). frequency should be 19.
PAGE 11
CONTROL LOGIC defined by t4. If more than 24 SCLKs were provided during DOUT mode, the DOUT/DRDY line would stay LOW until the time defined by t4. The internal data pointer for shifting data out on DOUT/DRDY is reset on the falling edge of the time defined by t1 and t4. This ensures that the first bit of data shifted out of the ADS1254 after DRDY mode is always the MSB of new data. The control logic is used for communications and control of the ADS1254.
PAGE 12
SERIAL INTERFACE The ADS1254 includes a simple serial interface that can be connected to microcontrollers and digital signal processors in a variety of ways. Communications with the ADS1254 can commence on the first detection of the DOUT/DRDY pulse after power up. It is important to note that the data from the ADS1254 is a 24-bit result transmitted MSB-first in Offset Two’s Complement format, as shown in Table IV.
PAGE 13
ADS1254 SBAS213B www.ti.com 13 t4 t1 t10 t2 t3 tDRDY t10 t2 t3 FIGURE 16. Power-Down Mode. DOUT/DRDY SCLK CLK tDRDY FIGURE 15. Synchronization Mode. DOUT/DRDY SCLK CLK FIGURE 14. DOUT/DRDY Timing.
PAGE 14
LAYOUT POWER SUPPLY The power supply should be well regulated and low noise. For designs requiring very high resolution from the ADS1254, power-supply rejection will be a concern. Avoid running digital lines under the device as they may couple noise onto the die. High-frequency noise can capacitively couple into the analog portion of the device and will alias back into the passband of the digital filter, affecting the conversion result. This clock noise will cause an offset error.
PAGE 15
Conversion Cycle—as used here, a conversion cycle refers to the time period between DOUT/DRDY pulses. Effective Resolution (ER)—of the ADS1254 in a particular configuration can be expressed in two different units: bits rms (referenced to output) and µVrms (referenced to input). Computed directly from the converter's output data, each is a statistical calculation based on a given number of results. Noise occurs randomly; the rms value represents a statistical measure that is one standard deviation.
PAGE 16
Revision History DATE REVISION PAGE SECTION 6/06 B 11 DOUT/DRDY DESCRIPTION Text changes to DOUT/DRDY section. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 16 ADS1254 www.ti.
PAGE 17
PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 19
PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS1254E/2K5 Package Package Pins Type Drawing SSOP DBQ 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 9.0 2.1 8.0 W Pin1 (mm) Quadrant 16.
PAGE 20
PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1254E/2K5 SSOP DBQ 20 2500 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.