ADS1255 ADS1256 SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 Very Low Noise, 24-Bit Analog-to-Digital Converter FEATURES D 24 Bits, No Missing Codes DESCRIPTION The ADS1255 and ADS1256 are extremely low-noise, 24-bit analog-to-digital (A/D) converters. They provide complete high-resolution measurement solutions for the most demanding applications. − All Data Rates and PGA Settings Up to 23 Bits Noise-Free Resolution ±0.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) ADS1255, ADS1256 UNIT AVDD to AGND −0.3 to +6 V DVDD to DGND −0.3 to +3.6 V AGND to DGND Input Current V mA 10, Continuous mA −0.3 to AVDD + 0.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 ELECTRICAL CHARACTERISTICS All specifications at −40°C to +85°C, AVDD = +5V, DVDD = +1.8V, fCLKIN = 7.68MHz, PGA = 1, and VREF = +2.5V, unless otherwise noted. PARAMETER Analog Inputs TEST CONDITIONS MIN TYP Full-scale input voltage (AINP − AINN) Absolute input voltage (AIN0-7, AINCOM to AGND) ±2VREF/PGA V AGND − 0.1 AVDD + 0.1 V Buffer on AGND AVDD − 2.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 ELECTRICAL CHARACTERISTICS (continued) All specifications at −40°C to +85°C, AVDD = +5V, DVDD = +1.8V, fCLKIN = 7.68MHz, PGA = 1, and VREF = +2.5V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 4.75 5.25 V 1.8 3.
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ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 PARAMETER MEASUREMENT INFORMATION CS t3 t2H t1 t10 SCLK t4 t5 t6 t2L t11 DIN t7 t8 t9 DOUT Figure 1.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 t 13 SCLK t13 t 12 t 14 t15 Figure 2. SCLK Reset Timing TIMING CHARACTERISTICS FOR FIGURE 2 SYMBOL (1) DESCRIPTION MIN MAX UNIT t12 SCLK reset pattern, first high pulse 300 500 τCLKIN(1) t13 SCLK reset pattern, low pulse t14 SCLK reset pattern, second high pulse t15 SCLK reset pattern, third high pulse τCLKIN 5 τCLKIN 550 750 τCLKIN 1050 1250 τCLKIN MIN MAX = master clock period = 1/fCLKIN.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS TA = +25°C, AVDD = 5V, DVDD = 1.8V, fCLKIN = 7.68MHz, PGA = 1, and VREF = 2.5V, unless otherwise noted.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS (continued) TA = +25°C, AVDD = 5V, DVDD = 1.8V, fCLKIN = 7.68MHz, PGA = 1, and VREF = 2.5V, unless otherwise noted.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS (continued) TA = +25°C, AVDD = 5V, DVDD = 1.8V, fCLKIN = 7.68MHz, PGA = 1, and VREF = 2.5V, unless otherwise noted. EFFECTIVE NUMBER OF BITS vs INPUT VOLTAGE 23 EFFECTIVE NUMBER OF BITS vs TEMPERATURE 23 PGA = 1 21 Data Rate = 30kSPS 20 Data Rate = 1kSPS 22 ENOB (rms) ENOB (rms) PGA = 1 Data Rate = 1kSPS 22 19 21 Data Rate = 30kSPS 20 19 18 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 18 5.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 OVERVIEW The ADS1255 and ADS1256 are very low-noise A/D converters. The ADS1255 supports one differential or two single-ended inputs and has two general-purpose digital I/Os. The ADS1256 supports four differential or eight single-ended inputs and has four general-purpose digital I/Os. Otherwise, the two units are identical and are referred to together in this data sheet as the ADS1255/6. Figure 5 shows a block diagram of the ADS1256.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 NOISE PERFORMANCE The ADS1255/6 offer outstanding noise performance that can be optimized by adjusting the data rate or PGA setting. As the averaging is increased by reducing the data rate, the noise drops correspondingly. The PGA reduces the input-referred noise when measuring lower level signals. Table 1 through Table 6 summarize the typical noise performance with the inputs shorted externally.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 Table 4. Input Referred Noise (μV, rms) with Buffer Off DATA RATE (SPS) 1 2 4 8 16 32 2.5 0.247 0.149 0.097 0.058 0.036 5 0.275 0.176 0.109 0.070 0.046 10 0.338 0.201 0.129 0.084 15 0.401 0.221 0.150 0.109 25 0.485 0.279 0.177 30 0.559 0.315 50 0.644 60 Table 6. Noise-Free Resolution (bits) with Buffer Off 64 DATA RATE (SPS) 1 2 4 8 16 32 64 0.031 0.027 2.5 23.0 22.4 22.0 21.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 INPUT MULTIPLEXER Figure 6 shows a simplified diagram of the input multiplexer. This flexible block allows any analog input pin to be connected to either of the converter differential inputs. That is, any pin can be selected as the positive input (AINP); likewise, any pin can be selected as the negative input (AINN). The pin selection is controlled by the multiplexer register.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 OPEN/SHORT SENSOR DETECTION ANALOG INPUT BUFFER The sensor detect current sources (SDCS) provide a means to verify the integrity of the external sensor connected to the ADS1255/6. When enabled, the SDCS supply a current (ISDC) of approximately 0.5μA, 2μA, or 10μA to the sensor through the input multiplexer. The SDCS bits in the ADCON register enable the SDCS and set the value of ISDC.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 The ADS1255/6 is a very high resolution converter. To further complement its performance, the low-noise PGA provides even more resolution when measuring smaller input signals. For the best resolution, set the PGA to the highest possible setting. This will depend on the largest input signal to be measured. The ADS1255/6 full-scale input voltage equals ±2VREF/PGA.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 The charging of the input capacitors draws a transient current from the sensor driving the ADS1255/6 inputs. The average value of this current can be used to calculate an effective impedance Zeff where Zeff = VIN / IAVERAGE. Figure 11 shows the input circuitry with the capacitors and switches of Figure 9 replaced by their effective impedances. These impedances scale inversely with the CLKIN frequency.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 DIGITAL FILTER The programmable low-pass digital filter receives the modulator output and produces a high-resolution digital output. By adjusting the amount of filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for higher data rate. The filter is comprised of two sections, a fixed filter followed by a programmable filter.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 Figure 14 and Figure 15 show the responses at the data rate extremes of 30kSPS and 2.5SPS respectively. Table 12 summarizes the first-notch frequency and −3dB bandwidth for the different data rate settings. Table 12.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 Table 13. Settling Time vs Data Rate 0 fD A T A = 3 0 k S P S DATA RATE (SPS) SETTLING TIME (t18) (ms) 30,000 0.21 15,000 0.25 7500 0.31 −80 3750 0.44 −100 2000 0.68 1000 1.18 f −20 C L K IN = 7 .6 8 M H z Gain (dB) −40 −60 −120 −140 0 1.92 3.84 5.76 7.68 Frequency (MHz) Figure 16. Frequency Response Out to 7.68MHz for Data Rate = 30kSPS 0 f D A T A = 2 .5 S P S f −20 C L K IN = 7 .
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 Step 3: Read the data from the previous conversion using the RDATA command. AINP −AINN Step 4: When DRDY goes low again, repeat the cycle by first updating the multiplexer register, then reading the previous data. SYNC/PDWN t 18 Table 14 gives the effective overall throughput (1/t19) when cycling the input multiplexer.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 If there is a step change on the input signal while continuously converting, performing a synchronization operation to start a new conversion is recommended. Otherwise, the next data will represent a combination of the previous and current input signal and should therefore be discarded. Figure 21 shows an example of readback in this situation.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 DATA FORMAT CLOCK OUTPUT (D0/CLKOUT) The ADS1255/6 output 24 bits of data in Binary Two’s Complement format. The LSB has a weight of 2VREF/(PGA(223 − 1)). A positive full-scale input produces an output code of 7FFFFFh and the negative full-scale input produces an output code of 800000h. The output clips at these codes for signals exceeding full-scale. Table 16 summarizes the ideal output codes for different input signals.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 CALIBRATION where α and β vary with data rate settings shown in Table 18 along with the ideal values (assumes perfect analog performance) for OFC and FSC. OFC is a Binary Two’s Complement number that can range from −8,388,608 to 8,388,607, while FSC is unipolar ranging from 0 to 16,777,215. Offset and gain errors can be minimized using the ADS1255/6 onboard calibration circuitry. Figure 23 shows the calibration block diagram.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 Self-Calibration Table 20. Self Gain Calibration Timing Self-calibration corrects internal offset and gain errors. During self-calibration, the appropriate calibration signals are applied internally to the analog inputs. SELFOCAL performs a self offset calibration. The analog inputs AINP and AINN are disconnected from the signal source and connected to AVDD/2.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 System Calibration System calibration corrects both internal and external offset and gain errors using the SYSOCAL and SYSGCAL commands. During system calibration, the appropriate calibration signals must be applied by the user to the inputs. SYSOCAL performs a system offset calibration. The user must supply a zero input differential signal. The ADS1255/6 then computes a value that will nullify the offset in the system.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 DATA READY (DRDY) STANDBY MODE The DRDY output is used as a status signal to indicate when conversion data is ready to be read. DRDY goes low when new conversion data is available. It is reset high when all 24 bits have been read back using Read Data (RDATA) or Read Data Continuous (RDATAC) command. It also goes high when the new conversion data is being updated. Do not retrieve during this update period as the data is invalid.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 APPLICATIONS INFORMATION GENERAL RECOMMENDATIONS The ADS1255 and ADS1256 are very high-resolution A/D converters. Getting the optimal performance from them requires careful attention to their support circuitry and printed circuit board (PCB) design. Figure 25 shows the basic connections for the ADS1255. It is recommended to use a single ground plane for both the analog and digital supplies.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 +5V 0.1μF OPA350 10kΩ 2.5V Input 47μF 0.1μF 100μF To VREFP Pin 4 of the ADS1255/6 1μF Figure 26. Recommended Voltage Reference Buffer Circuit DIGITAL INTERFACE CONNECTIONS The ADS1255/6 5V tolerant SPI-, QSPI™, and MICROWIRE™-compatible interface easily connects to a wide variety of microcontrollers. Figure 27 shows the basic connection to TI’s MSP430 family of low-power microcontrollers.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 REGISTER MAP The operation of the ADS1255/6 is controlled through a set of registers. Collectively, the registers contain all the information needed to configure the part, such as data rate, multiplexer settings, PGA setting, calibration, etc., and are listed in Table 23. Table 23.
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ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 DRATE: A/D Data Rate (Address 03h) Reset Value = F0h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 The 16 valid Data Rate settings are shown below. Make sure to select a valid setting as the invalid settings may produce unpredictable results.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 OFC0: Offset Calibration Byte 0, least significant byte (Address 05h) Reset value depends on calibration results. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 OFC07 OFC06 OFC05 OFC04 OFC03 OFC02 OFC01 OFC00 OFC1: Offset Calibration Byte 1 (Address 06h) Reset value depends on calibration results.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 COMMAND DEFINITIONS The commands summarized in Table 24 control the operation of the ADS1255/6. All of the commands are stand-alone except for the register reads and writes (RREG, WREG) which require a second command byte plus data. Additional command and data bytes may be shifted in without delay after the first command byte. The ORDER bit in the STATUS register sets the order of the bits within the output data.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 RDATAC: Read Data Continuous Description: Issue command after DRDY goes low to enter the Read Data Continuous mode. This mode enables the continuous output of new data on each DRDY without the need to issue subsequent read commands. After all 24 bits have been read, DRDY goes high. It is not necessary to read back all 24 bits, but DRDY will then not return high until new data is being updated.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 RREG: Read from Registers Description: Output the data from up to 11 registers starting with the register address specified as part of the command. The number of registers read will be one plus the second byte of the command. If the count exceeds the remaining registers, the addresses will wrap back to the beginning. 1st Command Byte: 0001 rrrr where rrrr is the address of the first register to read.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 SYSOCAL: System Offset Calibration Description: Performs a system offset calibration. The Offset Calibration Register (OFC) is updated after this operation. DRDY goes high at the beginning of the calibration. It goes low after the calibration completes and settled data is ready. Do not send additional commands after issuing this command until DRDY goes low indicating that the calibration is complete.
ADS1255 ADS1256 www.ti.com SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 Revision History DATE REV PAGE SECTION 09/12/13 K 20 Settling Time 09/12/13 K 22 09/12/13 K 22 09/12/13 K 26 Auto−Calibration Changed ADCON to STATUS 09/12/13 K 27 Data Ready Changed ADCON to STATUS 09/12/13 K 35 RDATAC: Read Data Continuous Changed STOPC to SDATAC.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 10-Sep-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE MATERIALS INFORMATION www.ti.com 10-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS1255IDBT SSOP DB 20 250 180.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 ADS1256IDBR SSOP DB 28 1000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 ADS1256IDBT SSOP DB 28 250 180.0 16.4 8.2 10.5 2.5 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 10-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1255IDBT SSOP DB 20 250 210.0 185.0 35.0 ADS1256IDBR SSOP DB 28 1000 367.0 367.0 38.0 ADS1256IDBT SSOP DB 28 250 210.0 185.0 35.
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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