Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External TSSOP 20

Programmable

DigitalFilter

2.5V

Reference

Modulator

VREFP VREFN REFOUTAVDD DVDD

DGND

AVSS

AINP

AINN

XTAL2

XTAL1/CLKIN

Control

and

Serial

Interface

Clock

Generator

Out-of-Range

Detection

RESETPWDN/

DRDY

SCLK

DIN

START

DOUT

Calibration

Engine

f /8

CLK

SYNCOUT

ADS1259

www.ti.com

SBAS424D –JUNE 2009– REVISED AUGUST 2011

Industrial, 14kSPS, 24-Bit Analog-to-Digital Converter

with Low-Drift Reference

Check for Samples: ADS1259

FEATURES

DESCRIPTION

The ADS1259 is a high-linearity, low-drift, 24-bit,

• 24 Bits, No Missing Codes

analog-to-digital converter (ADC) designed for the

• Output Data Rates From 10 To 14kSPS

needs of industrial process control, precision

• High Performance:

instrumentation, and other exacting applications.

Combined with a signal amplifier (such as the

– INL: 0.4ppm

PGA280), a high-resolution, high-accuracy

– Reference Drift: 2ppm/°C

measurement system is formed that is capable of

– Gain Drift: 0.5ppm/°C

digitizing a wide range of signals.

– Offset Drift: 0.05μV/°C

The converter uses a fourth-order, inherently stable,

– Noise: 0.7μV

RMS

at 60SPS

delta-sigma (ΔΣ) modulator that provides outstanding

noise and linearity performance. The data rates are

• Simultaneous 50/60Hz Rejection at 10SPS

programmable up to 14kSPS including 10SPS,

• Single-Cycle Settling

50SPS, and 60SPS that provide excellent normal

• Internal Oscillator

mode line-cycle rejection. The digital filter can be

programmed for a fast settling mode where the

• Out-of-Range Detection

conversions settle in a single cycle, or programmed

• Readback Data Integrity by Checksum and

for a high line-cycle rejection mode. A fast responding

Redundant Data Read Capability

input over-range detector flags the conversion data if

• SPI™-Compatible Interface

an input over-range should occur.

• Analog Supply: +5V or ±2.5V

The ADS1259 also provides an integrated low-noise,

• Digital Supply: +2.7V to +5V

very low drift 2.5V reference. The on-chip oscillator,

an external crystal, or an external clock can by used

• Low Power: 13mW

as the ADC clock source.

APPLICATIONS

Data and control communication are handled over a

4MHz, SPI-compatible interface capable of operating

• Industrial Process Control

with a minimum of three wires. Data integrity is

• Scientific Instrumentation

augmented by data bytes checksum and redundant

• Test and Measurement

data read capability. Conversions are synchronized

either by command or by pin.

Dissipating only 13mW in operation, the ADS1259

can be powered down, dissipating less than 25μW.

The ADS1259 is offered in a TSSOP-20 package and

is fully specified from –40°C to +105°C.

Summary of content (48 pages)

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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com Industrial, 14kSPS, 24-Bit Analog-to-Digital Converter with Low-Drift Reference Check for Samples: ADS1259 FEATURES DESCRIPTION • • • The ADS1259 is a high-linearity, low-drift, 24-bit, analog-to-digital converter (ADC) designed for the needs of industrial process control, precision instrumentation, and other exacting applications.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com ELECTRICAL CHARACTERISTICS Minimum/maximum specifications are at TA = –40°C to +105°C. Typical specifications are at TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 7.3728MHz, VREF = 2.5V, and fDATA = 60SPS, unless otherwise noted.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum/maximum specifications are at TA = –40°C to +105°C. Typical specifications are at TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 7.3728MHz, VREF = 2.5V, and fDATA = 60SPS, unless otherwise noted. ADS1259 PARAMETER TEST CONDITIONS MIN TYP ADS1259B MAX MIN TYP MAX UNIT CLOCK SOURCE (fCLK) Nominal frequency 7.3728 Accuracy ±0.2 ±2 2 7.3728 8 Frequency range 0.1 7.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com SPI TIMING CHARACTERISTICS tSPWH tSCLK tCSH CS tCSSC tSPWL SCLK tDIST DIN B7 B6 B5 B4 tDIHD DOUT B7 B3 B2 B1 B0 B3 B2 B1 B0 tDOPD B6 B5 B4 tCSDOD tDOHD tCSDOZ Figure 1. Serial Interface Timing TIMING REQUIREMENTS: SERIAL INTERFACE TIMING At TA = –40°C to +105°C and DVDD = 2.7V to 5.25V, unless otherwise noted. SYMBOL 6 MIN CS low to first SCLK: setup time (1) 50 tSCLK SCLK period 1.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = 3.3V, VREF = 2.5V, VREFN = AVSS, fCLK = 7.3728MHz, and fDATA = 60SPS, unless otherwise noted. NOISE DISTRIBUTION HISTOGRAM NOISE DISTRIBUTION HISTOGRAM 200 180 160 160 Data Rate = 10SPS Shorted Input 512 Samples 140 120 Occurrences 140 Occurrences Data Rate = 60SPS Shorted Input 512 Samples 120 100 80 60 100 80 60 40 40 20 20 0 -5.0 -4.5 -4.0 -3.5 -3.0 -2.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = 3.3V, VREF = 2.5V, VREFN = AVSS, fCLK = 7.3728MHz, and fDATA = 60SPS, unless otherwise noted. NOISE vs INPUT VOLTAGE NOISE vs INPUT VOLTAGE 7 7 Data Rate = 60SPS 6 5 5 Noise (mVrms) Noise (mVrms) Data Rate = 10SPS 6 4 3 Ratiometric Configuration Internal Reference CREFIN = 1mF 2 Internal Reference CREFIN = 1mF 4 2 REF5025 1 REF5025 1 0 -2.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = 3.3V, VREF = 2.5V, VREFN = AVSS, fCLK = 7.3728MHz, and fDATA = 60SPS, unless otherwise noted. OFFSET vs TEMPERATURE GAIN vs TEMPERATURE 100 500 5 Units 400 75 5 Units 300 Gain Error (ppm) 25 0 -25 200 100 0 -100 -200 -300 -50 -400 -75 -500 -55 -35 -15 5 25 45 65 85 105 125 -55 -35 5 -15 Figure 14. 45 65 85 105 125 Figure 15.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = 3.3V, VREF = 2.5V, VREFN = AVSS, fCLK = 7.3728MHz, and fDATA = 60SPS, unless otherwise noted. POWER-SUPPLY AND COMMON-MODE REJECTION vs FREQUENCY 140 CMR 3.5 DVDD DVDD 100 Power-Supply Current (mA) 120 PSR and CMR (dB) POWER-SUPPLY CURRENT vs TEMPERATURE 4.0 CMR AVDD, AVSS 80 AVDD 60 AVSS 40 20 3.0 AVDD, AVSS (Internal Reference On) 2.5 2.0 1.5 1.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = 3.3V, VREF = 2.5V, VREFN = AVSS, fCLK = 7.3728MHz, and fDATA = 60SPS, unless otherwise noted.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com OVERVIEW The ADS1259 is a high-linearity, low drift analog-to-digital converter (ADC) designed for the needs of industrial process control, precision instrumentation, and similar applications. The converter provides high-resolution, 24-bit output data at sample rates ranging from 10SPS to 14.4kSPS. Figure 32 shows a block diagram of the ADS1259. The device allows unipolar or bipolar analog power-supply configuration (AVDD – AVSS = 5V total).
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com NOISE PERFORMANCE MODULATOR The ADS1259 offers excellent noise performance that can be optimized by adjusting the data rate and by selection of the digital filter mode. As the averaging is increased by reducing the data rate, the noise drops correspondingly. Additionally, because the sinc2 digital filter provides more filtering than the sinc1 digital filter, sinc2 provides lower noise conversions.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 The ADS1259 modulator is inherently stable and therefore has predictable recovery behavior resulting from an input overdrive condition. The modulator does not exhibit the self-resetting behavior of other modulator types, which often results in unstable output conversion results when overdriven.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com ANALOG INPUTS (AINP, AINN) ESD diodes protect the analog inputs. To keep these diodes from turning on, make sure the voltages on the input pins do not go below AVSS by more than 300mV, and likewise do not exceed AVDD by more than 300mV. The ADS1259 measures the differential input signal VIN = (AINP – AINN) against the differential reference VREF = (VREFP – VREFN) using internal capacitors that are continuously charged and discharged.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com REFERENCE the ADC reference input pins, VREFP and VREFN. (Note that these device pins are not intended to drive external circuits.) An external 1μF capacitor, connected from VREFP to VREFN, is recommended for noise reduction. The capacitor can be increased for increased noise filtering, but the settling time of the reference may also increase. The settling time should be considered upon activating the internal reference.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com Reference Drift External Reference The ADS1259 internal reference is designed for minimal drift error, which is defined as the change in reference voltage over temperature. The drift is calculated using the box method, as described by Equation 2. VREFMAX - VREFMIN Drift = x 106 (ppm) VREFNOM ´ Temp Range To select the ADS1259 for external reference operation, set the EXTREF register bit = 1 (default).
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com DIGITAL FILTER The programmable low-pass digital filter receives the modulator output and produces a high-resolution digital output. By adjusting the amount of filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for higher data rate.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com The sinc5 filter produces wide notches at fCLK/512 and multiples thereof. At these frequencies the filter has zero gain. Figure 40 shows the response data rate = 14.4kSPS. -20 Magnitude (dB) With decimation of the second stage, the wide notches produced by the sinc5 filter remain, but a number of narrow notches are superimposed in the response. The first of the notches occur at the data rate.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com ALIASING CLOCK SOURCE The low-pass characteristic of the digital filter repeats at multiples of the modulator rate (fMOD = fCLK/8). Figure 43 shows the responses plotted out to 7.3728MHz at the data rate of 14.4kSPS. Notice how the responses near dc, 0.9216MHz, 1.8432MHz, 2.7698MHz, etc, are the same as given by f = NfMOD ± fDATA where N = 0, 1, 2, etc.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com External Clock SYNCOUT Figure 46 shows the external clock connection. The clock is applied to XTAL1/CLKIN and XTAL2 floats. Make sure a clean clock input is applied to the ADS1259, free of overshoot and glitches. A series resistor often helps to reduce overshoot and should be placed close to the driving end of the clock source.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com RESET/PWDN RESET The RESET/PWDN pin has two functions: device power-down and device reset. Momentarily holding the pin low resets the device and holding the pin low for 216 fCLK cycles activates the Power-Down mode. There are three methods to reset the ADS1259: cycle the power supplies, take RESET/PWDN low, or send the RESET opcode command. When using the RESET/PWDN pin, take it low to force a reset.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com START START is a digital input that controls the ADS1259 conversions. Conversions are started when START is taken high and are stopped when START is taken low. If START is toggled during a conversion, the conversion is restarted. DRDY goes high when START is taken high. Figure 50 andTable 7 show the START timing. Note that reasserting START within 22 tCLK cycles of the DRDY falling edge causes DRDY to fall soon after.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com Pulse Control Mode (PULSE Bit = 1) Settling Time Using START In the Pulse Control mode, the ADS1259 performs a single conversion when either the START pin is taken high or when the START command is sent. As seen in Figure 52, DRDY goes high when the conversion is started. When the conversion is complete, DRDY goes low and further conversions are halted.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com Settling Time While Continuously Converting OFFSET AND GAIN If there is a step change on the input signal while continuously converting, the next data represent a combination of the previous and current input signal and should therefore be discarded; see Figure 54 for this step change. Table 10 shows the number of conversion cycles for completely settled data while continuously converting.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com Table 11. Offset Calibration Values OFFSET AND FULL-SCALE CALIBRATION REGISTERS The conversion data are scaled by offset and gain registers before yielding the final output code. As shown in Figure 55, the output of the digital filter is first subtracted by the offset register (OFC) and then multiplied by the full-scale register (FSC).
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com CALIBRATION The ADS1259 has commands to correct for system offset and gain errors. Calibration can be performed at any time the ADS1259 and associated circuitry (such as the input amplifier, external reference, power supplies, etc) have stabilized. Options include calibrating after power-up, after temperature changes, or calibration at regular intervals.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com SERIAL INTERFACE DATA INPUT (DIN) The SPI-compatible serial interface consists of four signals: CS, SCLK, DIN, and DOUT or three signals, in which case CS may be tied low. The interface is used to read conversion data, configure registers, and control the ADS1259 operation. DIN is the input data pin and is used with SCLK to send data to the ADS1259 (opcode commands and register data).
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com DATA FORMAT DATA CHECKSUM BYTE AND FLAG BIT The ADS1259 outputs 24 bits of conversion data in binary twos complement format, MSB first. The data LSB has a weight of VREF/(223 – 1). A positive full-scale input produces an output code of 7FFFFFh and the negative full-scale input produces an output code of 800000h. The output clips at these codes for signals that exceed full-scale.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com DATA RETRIEVAL New conversion data are available when DRDY goes low. Read the data within 20 fCLK cycles of the next DRDY falling edge or the data are incorrect. Do not read data during this interval. The conversion data may be read in two ways: Data Read in Continuous mode and Data Read in Stop Continuous mode.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com Data Read Operation in Stop Continuous Mode As shown in Figure 61, after sending the RDATA command the data are shifted out on DOUT on the rising edges of SCLK. The MSB is clocked out on the first rising edge of SCLK. In Gate Control mode, DRDY returns to high on the first falling edge of SCLK. In Pulse Control mode, DRDY remains low until a new conversion is started.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com COMMAND DEFINITIONS The commands summarized in Table 19 control and configure the operation of the ADS1259. The commands are stand-alone, except for the register read and register write operations which require a second command byte plus data. CS can be taken high or held low between opcode commands but must stay low for the entire command operation.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com RDATA: Read Data Description: Issue this command opcode after DRDY goes low to read the conversion result (in Stop Read Data Continuous mode). See the Read Data Mode section for more details. RREG: Read from Registers Description: These opcode bytes read register data. The Register Read command is a two-byte opcode followed by the output of the register data. The first byte contains the command opcode and the register address.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com WREG: Write to Register Description: These two opcode bytes write register data. The Register Write command is a two-byte opcode followed by the register data. The first byte contains the command opcode and the register address. The second byte of the opcode specifies the number of registers to write – 1. First opcode byte: 0100 rrrr, where rrrr is the starting register address.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com REGISTER MAP The operation of the ADS1259 is controlled through a set of registers. Collectively, the registers contain all the information needed to configure the part, such as data rate, calibration, etc. Table 20 shows the register map. Table 20.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com CONFIG1: CONFIGURATION REGISTER 1 (Address = 1h) 7 6 5 4 3 2 1 0 FLAG CHKSUM 0 SINC2 EXTREF DELAY2 DELAY1 DELAY0 Reset value = 00001000b.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com CONFIG2: CONFIGURATION REGISTER 2 (Address = 2h) 7 6 5 4 3 2 1 0 DRDY EXTCLK SYNCOUT PULSE 0 DR2 DR1 DR0 Reset value = XX000000b. Bit 7 DRDY: Data ready (read-only) This bit duplicates the state of the DRDY pin. Poll this bit to indicate that data are ready. When DRDY is low, data are ready.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com OFC0: OFFSET CALIBRATION BYTE 0, LEAST SIGNIFICANT BYTE (Address = 3h) 7 6 5 4 3 2 1 0 OFC07 OFC06 OFC05 OFC04 OFC03 OFC02 OFC01 OFC00 Reset value = 00000000b. OFC1: OFFSET CALIBRATION BYTE 1 (Address = 4h) 7 6 5 4 3 2 1 0 OFC15 OFC14 OFC13 OFC12 OFC11 OFC10 OFC09 OFC08 Reset value = 00000000b.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com BASIC CONNECTION The ADS1259 basic connections are shown in Figure 64. The diagram shows the ADS1259 operating with an internal oscillator and with internal reference. Dual ±2.5V analog power supplies are also shown. Pins 6-9 are the SPI port connection. The remaining digital I/O pins connect to the controller I/O. Note that the minimum configuration of the digital I/O may include only SCLK, DIN, and DOUT. +2.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com SYNCOUT Pin Connect the SYNCOUT pin to the SYNCIN pin of the PGA280, using a 4.7kΩ series resistor (placed close to the ADS1259). The 1MΩ pull-down resistor is required when the ADS1259 is in power-down mode. RESET/PWDN Pin This pin must be high in normal operation. If it is desired to completely power down the device, or to have a hardware reset control, then connect this pin to a controller.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com 3. Optional readback verification of the register data READ register command: <20h>, <08> The nine bytes of readback data that follow represent the nine register bytes. 4. Take the START pin high or send the START command to start conversions. 5. Optionally, send the RDATAC command <10h>. This permits reading of conversion data without the need of the read data command.
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ADS1259 SBAS424D – JUNE 2009 – REVISED AUGUST 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (March 2010) to Revision D Page • Added Internal Voltage Reference, Long-term stability parameter to Electrical Characteristics table ................................. 3 • Added Internal Voltage Reference, Thermal hysteresis parameter and footnote 11 to Electrical Characteristics table ......
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS1259BIPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 ADS1259IPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1259BIPWR TSSOP PW 20 2000 367.0 367.0 38.0 ADS1259IPWR TSSOP PW 20 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.