Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External TSSOP 16

SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007

  

 



FEATURES

D 105kSPS Data Rate

D AC Performance:

51kHz Bandwidth

109dB SNR (High-Resolution Mode)

−108dB THD

D DC Accuracy:

1.8µV/°C Offset Drift

2ppm/°C Gain Drift

D Selectable Operating Modes:

High-Speed: 105kSPS Data Rate

High-Resolution: 109dB SNR

Low-Power: 35mW Dissipation

D Power-Down Control

D Digital Filter:

Linear Phase Response

Passband Ripple: ±0.005dB

Stop Band Attenuation: 100dB

D Internal Offset Calibration On Command

D Selectable SPIt or Frame Sync Serial Interface

D Designed for Multichannel Systems:

Daisy-Chainable Serial Interface

Easy Synchronization

D Simple Pin-Driven Control

D Modulator Output Option

D Specified from −40°C to +105°C

D Analog Supply: 5V

D Digital Supply: 1.8V to 3.3V

APPLICATIONS

D Vibration/Modal Analysis

D Acoustics

D Dynamic Strain Gauges

D Pressure Sensors

D Test and Measurement

DESCRIPTION

The ADS1271 is a 24-bit, delta-sigma analog-to-digital

converter (ADC) with a data rate up to 105kSPS. It offers

a unique combination of excellent DC accuracy and

outstanding AC performance. The high-order,

chopper-stabilized modulator achieves very low drift with

low in-band noise. The onboard decimation filter

suppresses modulator and signal out-of-band noise. The

ADS1271 provides a usable signal bandwidth up to 90%

of the Nyquist rate with less than 0.005dB of ripple.

Traditionally, industrial delta-sigma ADCs offering good

drift performance use digital filters with large passband

droop. As a result, they have limited signal bandwidth and

are mostly suited for DC measurements. High-resolution

ADCs in audio applications offer larger usable bandwidths,

but the offset and drift specification are significantly

weaker than their industrial counterparts. The ADS1271

combines these converters, allowing high-precision

industrial measurement with excellent DC and AC

specifications ensured over an extended industrial

temperature range.

Three operating modes allow for optimization of speed,

resolution, and power. A selectable SPI or a frame-sync

serial interface provides for convenient interfacing to

microcontrollers or DSPs. The output from the modulator

is accessible for external digital filter applications. All

operations, including internal offset calibration, are

controlled directly by pins; there are no registers to

program.

∆Σ

Modulator

Digital

Filter

VREFP VREFN AVDD DVDD

DRDY/FSYNC

SCLK

DOUT

DIN

FORMAT

AINP

AINN

Serial

Interface

Control

Logic

DGNDAGND

SYNC/PDWN

MODE

CLK

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

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SPI is a trademark of Motorola Inc. All other trademarks are the property of their respective owners.

Summary of content (38 pages)

PAGE 1
SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 FEATURES D 105kSPS Data Rate D AC Performance: DESCRIPTION The ADS1271 is a 24-bit, delta-sigma analog-to-digital converter (ADC) with a data rate up to 105kSPS. It offers a unique combination of excellent DC accuracy and outstanding AC performance. The high-order, chopper-stabilized modulator achieves very low drift with low in-band noise.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) ADS1271 UNIT AVDD to AGND −0.3 to +6.0 V DVDD to DGND −0.3 to +3.6 V AGND to DGND Input Current −0.3 to +0.3 V 100, Momentary mA 10, Continuous mA Analog Input to AGND −0.3 to AVDD + 0.3 V Digital Input or Output to DGND −0.3 to DVDD + 0.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS All specifications at TA = −40°C to +105°C, AVDD = +5V, DVDD = +1.8V, fCLK = 27MHz, VREFP = 2.5V, and VREFN = 0V, unless otherwise noted. Specified values for ADS1271 and ADS1271B (high-grade version) are the same, except where shown in BOLDFACE type. ADS1271 PARAMETER TEST CONDITIONS MIN TYP ADS1271B MAX MIN AVDD + 0.1 AGND – 0.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = −40°C to +105°C, AVDD = +5V, DVDD = +1.8V, fCLK = 27MHz, VREFP = 2.5V, and VREFN = 0V, unless otherwise noted. Specified values for ADS1271 and ADS1271B (high-grade version) are the same, except where shown in BOLDFACE type. ADS1271 PARAMETER TEST CONDITIONS MIN TYP 2.0 2.5 ADS1271B MAX MIN TYP 2.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 PIN ASSIGNMENTS PW PACKAGE TSSOP-16 (TOP VIEW) AINP 1 16 VREFP AINN 2 15 VREFN AGND 3 14 DGND AVDD 4 13 DVDD ADS1271 MODE 5 12 CLK FORMAT 6 11 SCLK SYNC/PDWN 7 10 DRDY/FSYNC DIN 8 9 DOUT Terminal Functions PIN NAME NO.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 TIMING CHARACTERISTICS: SPI FORMAT tCLK t CPW • • tCPW CLK tCD • tCONV DRDY t SD t DS tS tSPW SCLK tSPW t DDO DOUT Bit 23 (MSB) tDOPD t DOHD Bit 22 t DIST Bit 21 t DIHD DIN TIMING REQUIREMENTS: SPI FORMAT For TA = −40°C to +105°C and DVDD = 1.65V to 3.6V.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 TIMING CHARACTERISTICS: FRAME-SYNC FORMAT t CPW tCLK CLK t CPW tCF tFRAME tFPW tFPW FSYNC tFS tS t SPW tSF SCLK tSPW tDDO DOUT Bit 23 (MSB) tDOPD tDOHD Bit 22 tDIST Bit 21 tDIHD DIN TIMING REQUIREMENTS: FRAME-SYNC FORMAT for TA = −40°C to +105°C and DVDD = 1.65V to 3.6V.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS TA = 25°C, AVDD = 5V, DVDD = 1.8V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, unless otherwise noted. OUTPUT SPECTRUM OUTPUT SPECTRUM 0 Amplitude (dB) −40 High−Speed Mode fIN = 1kHz, −0.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) TA = 25°C, AVDD = 5V, DVDD = 1.8V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, unless otherwise noted.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) TA = 25°C, AVDD = 5V, DVDD = 1.8V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, unless otherwise noted.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) TA = 25°C, AVDD = 5V, DVDD = 1.8V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, unless otherwise noted.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) TA = 25°C, AVDD = 5V, DVDD = 1.8V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, unless otherwise noted.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) TA = 25°C, AVDD = 5V, DVDD = 1.8V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, unless otherwise noted. NOISE vs DVDD 20 18 18 16 16 14 14 12 High−Speed 10 Low−Power 8 High−Resolution 6 RMS Noise (µV) RMS Noise (µV) NOISE vs AVDD 20 Low−Power 10 8 6 4 4 2 2 0 4.75 High−Speed 12 High−Resolution 0 4.85 4.95 5.05 5.15 5.25 1.6 1.8 2.0 2.2 2.6 2.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) TA = 25°C, AVDD = 5V, DVDD = 1.8V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, unless otherwise noted. OFFSET AND GAIN ERROR vs VREF NOISE vs VREF 100 400 75 300 12 200 Offset 25 100 0 0 Gain Error −25 −100 See Electrical Characteristics for VREF Operating Range −50 0.5 1.0 8 Low−Power 6 High−Resolution 4 2 See Electrical Characteristics for VREF Operating Range −200 3.0 0 VREF (V) 1.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 OVERVIEW The ADS1271 is a 24-bit, delta-sigma ADC. It offers the combination of outstanding DC accuracy and superior AC performance. Figure 43 shows the block diagram for the ADS1271. The ADS1271 converter is comprised of an advanced, 6th-order, chopper-stabilized, delta-sigma modulator followed by a low-ripple, linear phase FIR filter.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 ANALOG INPUTS (AINP, AINN) The ADS1271 measures the differential input signal VIN = (AINP – AINN) against the differential reference VREF = (VREFP – VREFN). The most positive measurable differential input is +VREF, which produces the most positive digital output code of 7FFFFFh. Likewise, the most negative measurable differential input is −VREF, which produces the most negative digital output code of 800000h.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 VOLTAGE REFERENCE INPUTS (VREFP, VREFN) The voltage reference for the ADS1271 ADC is the differential voltage between VREFP and VREFN: VREF = (VREFP−VREFN). The reference inputs use a structure similar to that of the analog inputs with the equivalent circuitry on the reference inputs shown in Figure 47. As with the analog inputs, the load presented by the switched capacitor can be modeled with an effective impedance, as shown in Figure 48.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 CLOCK INPUT (CLK) The ADS1271 requires an external clock signal to be applied to the CLK input pin. As with any high-speed data converter, a high-quality, low-jitter clock is essential for optimum performance. Crystal clock oscillators are the recommended clock source. Make sure to avoid excess ringing on the clock input; keeping the clock trace as short as possible using a 50Ω series resistor will help.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 MODE SELECTION (MODE) The ADS1271 supports three modes of operation: High-Speed, High-Resolution, and Low-Power. The mode selection is determined by the status of the digital input MODE pin, as shown in Table 5. A high impedance, or floating, condition allows the MODE pin to support a third state. The ADS1271 constantly monitors the status of the MODE pin during operation and responds to a change in status after 12,288 CLK periods.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 SYNCHRONIZATION Figure 51 shows the timing requirement for Frame-Sync format. The SYNC/PDWN pin has two functions. When pulsed, it synchronizes the start of conversions and, if held low for more than 219 CLK cycles (tSYN), places the ADS1271 in Power-Down mode. The SYNC/PDWN pin can be left high for continuous data acquisition. See the Power-Down and Offset Calibration section for more details.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 POWER-DOWN AND OFFSET CALIBRATION In addition to controlling synchronization, the SYNC/PDWN pin also serves as the control for Power-Down mode and offset calibration. To enter this mode, hold the SYNC/PDWN pin low for at least 219 CLK periods. While in Power-Down mode, both the analog and digital circuitry are completely deactivated. The digital inputs are internally disabled so that is not necessary to shut down CLK and SCLK.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 POWER-UP SEQUENCE 0 FREQUENCY RESPONSE −20 Amplitude (dB) The analog and digital supplies should be applied before any analog or digital input is driven. The power supplies may be sequenced in any order. Once the supplies and the voltage reference inputs have stabilized, data can be read from the device. The digital filter sets the overall frequency response.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 High-Resolution Mode 0 −1 Amplitude (dB) −2 −3 −4 −5 −6 −7 −8 −9 −10 0.45 0.47 0.49 0.51 0.53 0.55 Normalized Input Frequency (fIN/f DATA) The oversampling ratio is 128 in High-Resolution mode. Figure 58 shows the frequency response in High-Resolution mode normalized to fDATA. Figure 59 shows the passband ripple, and the transition from passband to stop band is illustrated in Figure 60.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 PHASE RESPONSE 0 The ADS1271 incorporates a multiple stage, linear phase digital filter. Linear phase filters exhibit constant delay time versus input frequency (constant group delay). This means the time delay from any instant of the input signal to the same instant of the output data is constant and is independent of input signal frequency. This behavior results in essentially zero phase errors when analyzing multi-tone signals.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 DATA FORMAT The ADS1271 outputs 24 bits of data in two’s complement format. A positive full-scale input produces an output code of 7FFFFFh, and the negative full-scale input produces an output code of 800000h. The output clips at these codes for signals exceeding full-scale. Table 9 summarizes the ideal output codes for different input signals. Table 9.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 FRAME-SYNC SERIAL INTERFACE DRDY/FSYNC Frame-Sync format is similar to the interface often used on audio ADCs. It operates in slave fashion—the user must supply framing signal FSYNC (similar to the left/right clock on stereo audio ADCs) and the serial clock SCLK (similar to the bit clock on audio ADCs). The data is output MSB first or left-justified.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 DAISY-CHAINING Multiple ADS1271s can be daisy-chained together to simplify the serial interface connections. The DOUT of one ADS1271 is connected to the DIN of the next ADS1271. The first DOUT provides the output data and the last DIN in the chain is connected to ground. A common SCLK is used for all the devices in the daisy chain. Figure 64 shows an example of a daisy chain with four ADS1271s.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 MODULATOR OUTPUT The ADS1271 incorporates a 6th-order, single-bit, chopper-stabilized modulator followed by a multi-stage digital filter, which yields the conversion results. The data stream output of the modulator is available directly, bypassing the internal digital filter. In this mode, an external digital filter implemented in an ASIC, FPGA, or similar device is required.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 APPLICATION INFORMATION 5. Reference Inputs: It is recommended to use a minimum 10µF tantalum with a 0.1µF ceramic capacitor directly across the reference inputs, VREFP and VREFN. The reference input should be driven by a low-impedance source. For best performance, the reference should have less than 3µVRMS broadband noise. For references with noise higher than this, external reference filtering may be necessary. 6.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 1kΩ 10nF (2) +5V ADS1271 +5V 0.1µF 100Ω 1 AINP Differential Inputs 100pF OPA350 VREFP 16 + 1nF 10µF 100Ω 1kΩ 100µF 2 AINN VREFN 15 3 AGND DGND 14 4 AVDD DVDD 13 + 0.47µF REF3125 0.1µF 0.1µF 100pF +5V 0.1µF + 10µF 1.8V to 3.3V (1) 10µF 0.1µF 50Ω 5 MODE Tie to Either DVDD or GND 27MHz Clock Source CLK 12 50Ω 6 FORMAT SCLK 11 50Ω 7 SYNC/ DRDY/ 10 PDWN FSYNC 50Ω 50Ω 50Ω 8 DIN DOUT NOTE: (1) 1.8V recommended.
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www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 Revision History DATE REV PAGE SECTION DESCRIPTION 10/07 F 25 SCLK (SPI Format) Added final paragraph to section. 9/07 E 20 Synchronization Added sentence to 1st paragraph regarding SYNC/PDWN left high. 2 Absolute Maximum Ratings Deleted lead temperature. 7 Timing Characteristics: Frame-Sync Format Changed tDDO parameter from “falling edge” to “rising edge.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 21-May-2010 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS1271IBPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 ADS1271IPWR TSSOP PW 16 2500 330.0 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1271IBPWR TSSOP PW 16 2000 367.0 367.0 35.0 ADS1271IPWR TSSOP PW 16 2500 367.0 367.0 35.
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