ADS1291 ADS1292 ADS1292R www.ti.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 ELECTRICAL CHARACTERISTICS Minimum and maximum specifications apply from –40°C to +85°C. Typical specifications are at +25°C. All specifications are at DVDD = 1.8 V, AVDD – AVSS = 3 V (1), VREF = 2.42 V, external fCLK = 512 kHz, data rate = 500 SPS, CFILTER = 4.7 nF (2), and gain = 6, unless otherwise noted.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum and maximum specifications apply from –40°C to +85°C. Typical specifications are at +25°C. All specifications are at DVDD = 1.8 V, AVDD – AVSS = 3 V(1), VREF = 2.42 V, external fCLK = 512 kHz, data rate = 500 SPS, CFILTER = 4.7 nF(2), and gain = 6, unless otherwise noted.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 ELECTRICAL CHARACTERISTICS (continued) Minimum and maximum specifications apply from –40°C to +85°C. Typical specifications are at +25°C. All specifications are at DVDD = 1.8 V, AVDD – AVSS = 3 V(1), VREF = 2.42 V, external fCLK = 512 kHz, data rate = 500 SPS, CFILTER = 4.7 nF(2), and gain = 6, unless otherwise noted.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum and maximum specifications apply from –40°C to +85°C. Typical specifications are at +25°C. All specifications are at DVDD = 1.8 V, AVDD – AVSS = 3 V(1), VREF = 2.42 V, external fCLK = 512 kHz, data rate = 500 SPS, CFILTER = 4.7 nF(2), and gain = 6, unless otherwise noted.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 PARAMETER MEASUREMENT INFORMATION NOISE MEASUREMENTS The ADS1291, ADS1292, and ADS1292R noise performance can be optimized by adjusting the data rate and PGA setting. As the averaging is increased by reducing the data rate, the noise drops correspondingly. Increasing the programmable gain amplifier (PGA) value reduces the input-referred noise, which is particularly useful when measuring low-level biopotential signals.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com Table 3. Input-Referred Noise (μVRMS / μVPP) 3-V Analog Supply and 2.42-V Reference (1) PGA GAIN = 6 DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) μVRMS μVPP 000 125 32.75 0.5 3.0 001 250 65.5 0.7 010 500 131 011 1000 100 (1) PGA GAIN = 8 SNR NOISEFREE BITS SNR NOISEFREE BITS ENOB μVRMS μVPP 115.9 18.04 19.26 0.4 2.6 ENOB 114.0 17.82 4.1 112.8 17.58 18.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 Table 6. Input-Referred Noise (μVRMS / μVPP) 5-V Analog Supply and 4.033-V Reference (1) PGA GAIN = 3 DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) μVRMS μVPP 000 125 32.75 0.6 4.2 001 250 65.5 0.9 010 500 131 011 1000 100 (1) PGA GAIN = 4 SNR NOISEFREE BITS SNR NOISEFREE BITS ENOB μVRMS μVPP 123.4 19.28 20.50 0.5 3.6 ENOB 122.3 19.08 5.7 120.7 18.82 20.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com TIMING CHARACTERISTICS tCLK CLK tCSSC tSCLK SCLK tCSH tSDECODE CS 1 tSPWL tSPWH 3 2 8 1 tDIHD tDIST tSCCS 3 2 8 tDOPD DIN tCSDOZ tCSDOD Hi-Z Hi-Z DOUT NOTE: SPI settings are CPOL = 0 and CPHA = 1. Figure 1. Serial Interface Timing Timing Requirements For Figure 1 (1) 2.7 V ≤ DVDD ≤ 3.
ADS1291 ADS1292 ADS1292R www.ti.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.42 V, VREFN = AVSS, external clock = 512 kHz, data rate = 500 SPS, CFILTER = 4.7 nF, and gain = 6, unless otherwise noted. INPUT-REFERRED NOISE NOISE HISTOGRAM 4 1200 1000 2 1 Occurences Input−Referred Noise (µV) 3 0 −1 800 600 400 −2 200 −3 Peak−to−Peak Over 10 seconds = 8 µV G001 4 3 3.5 2 2.5 1 1.5 0 0.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.42 V, VREFN = AVSS, external clock = 512 kHz, data rate = 500 SPS, CFILTER = 4.7 nF, and gain = 6, unless otherwise noted. PSRR vs FREQUENCY THD vs FREQUENCY −55 Data Rate = 8 kSPS, −0.5 dBFS Data Rate = 8 kSPS, −0.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.42 V, VREFN = AVSS, external clock = 512 kHz, data rate = 500 SPS, CFILTER = 4.7 nF, and gain = 6, unless otherwise noted. OFFSET vs PGA GAIN (Absolute Value) TEST SIGNAL AMPLITUDE ACCURACY 300 60 Data from 96 devices, Two lots 250 Number of Bins Offset (uV) 200 150 100 40 20 50 G013 0.6 0.5 0.4 0.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com OVERVIEW The ADS1291, ADS1292, and ADS1292R are low-power, multichannel, simultaneously-sampling, 24-bit deltasigma (ΔΣ) analog-to-digital converters (ADCs) with integrated programmable gain amplifiers (PGAs). These devices integrate various electrocardiogram (ECG)-specific functions that make them well-suited for scalable ECG, sports, and fitness applications.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 THEORY OF OPERATION This section contains details of the ADS1291, ADS1292, and ADS1292R internal functional elements. The analog blocks are discussed first followed by the digital interface. Blocks implementing ECG-specific functions are covered in the end.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 Auxiliary Differential Input (RESP_MODN/IN3N, RESP_MODN/IN3P) In applications where the respiration modulator output is not used, the RESP_MODN/IN3N and RESP_MODN/IN3P signals can be used as a third multiplexed differential input channel. These inputs can be multiplexed to either of the ADC channels. Temperature Sensor (TEMPP, TEMPN) The ADS1291, ADS1292, and ADS1292R contain an on-chip temperature sensor.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com ANALOG INPUT The ADS1291, ADS1292, and ADS1292R analog input is fully differential. Assuming PGA = 1, the differential input (INP – INN) can span between –VREF to +VREF. Note that the absolute range for INP and INN must be between AVSS – 0.3 V and AVDD + 0.3 V. Refer to Table 10 for an explanation of the correlation between the analog input and the digital codes.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 PGA SETTINGS AND INPUT RANGE The PGA is a differential input or differential output amplifier, as shown in Figure 23. It has seven gain settings (1, 2, 3, 4, 6, 8, and 12) that can be set by writing to the CHnSET register (see the CH1SET and CH2SET Registers in the Register Map section for details). The ADS1291, ADS1292, and ADS1292R have CMOS inputs and hence have negligible current noise.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com Special care must be taken in PCB layout to minimize the parasitic capacitance CP1 / CP2. The absolute value of these capacitances must be less than 20 pF. Ideally, CFILTER should be placed right at the pins to minimize these capacitors. Mismatch between these capacitors will lead to CMRR degradation. Assuming everything else is perfectly matched, the 60-Hz CMRR as a function of this mismatch is given by Equation 5.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 ADC ΔΣ Modulator Power Spectral Density (dB) Each channel of the ADS1291, ADS1292, and ADS1292R has a 24-bit ΔΣ ADC. This converter uses a secondorder modulator optimized for low-power applications. The modulator samples the input signal at the rate of fMOD = fCLK / 4 or fCLK / 16, as determined by the CLK_DIV bit. In both cases, the sampling clock has a typical value of 128 kHz.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com 0 0 -20 -0.5 -40 -1 Gain (dB) Gain (dB) The sinc filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these frequencies, the filter has infinite attenuation. Figure 26 shows the sinc filter frequency response and Figure 27 shows the sinc filter roll-off. With a step change at input, the filter takes 3 tDR to settle.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 10 DR[2:0] = 110 DR[2:0] = 000 -10 Gain (dB) -30 -50 -70 -90 -110 -130 0 0.5 1 1.5 2 2.5 3 3.5 4 Normalized Frequency (fIN/fMOD) Figure 30. Transfer Function of On-Chip Decimation Filters Until 4fMOD for DR[2:0] = 000 and DR[2:0] = 110 REFERENCE Figure 31 shows a simplified block diagram of the ADS1291, ADS1292, and ADS1292R internal reference. The reference voltage is generated with respect to AVSS.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com 100 kW 10 pF +5 V 0.1 mF 100 W +5 V VIN To VREFP Pin OPA211 100 W 10 mF OUT 22 mF REF5025 TRIM 0.1 mF 100 mF 22 mF Figure 32.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 CLOCK The ADS1291, ADS1292, and ADS1292R provide two different methods for device clocking: internal and external. Internal clocking is ideally suited for low-power, battery-powered systems. The internal oscillator is trimmed for accuracy at room temperature. Over the specified temperature range the accuracy varies; see the Electrical Characteristics.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com DATA FORMAT The ADS1291, ADS1292, and ADS1292R outputs 24 bits of data per channel in binary twos complement format, MSB first. The LSB has a weight of VREF / (223 – 1). A positive full-scale input produces an output code of 7FFFFFh and the negative full-scale input produces an output code of 800000h. The output clips at these codes for signals exceeding full-scale.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 Data Input (DIN) The data input pin (DIN) is used along with SCLK to communicate with the ADS1291, ADS1292, and ADS1292R (opcode commands and register data). The device latches data on DIN on the SCLK falling edge. Data Output (DOUT) The data output pin (DOUT) is used with SCLK to read conversion and register data from the ADS1291, ADS1292, and ADS1292R. Data on DOUT are shifted out on the SCLK rising edge.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com Figure 35 shows the relationship between DRDY, DOUT, and SCLK during data retrieval (in case of an ADS1291, ADS1292, and ADS1292R with a selected data rate that gives 24-bit resolution). DOUT is latched out at the SCLK rising edge. DRDY is pulled high at the SCLK falling edge.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 START The START pin must be set high or the START command sent to begin conversions. When START is low or if the START command has not been sent, the device does not issue a DRDY signal (conversions are halted). When using the START opcode to control conversion, hold the START pin low. The ADS1291, ADS1292, and ADS1292R feature two modes to control conversion: continuous mode and single-shot mode.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com Continuous Mode Conversions begin when the START pin is taken high or when the START opcode command is sent. As seen in Figure 38, the DRDY output goes high when conversions are started and goes low when data are ready. Conversions continue indefinitely until the START pin is taken low or the STOP opcode command is transmitted.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 Single-Shot Mode The single-shot mode is enabled by setting the SINGLE_SHOT bit in the CONFIG1 register to '1'. In single-shot mode, the ADS1291, ADS1292, and ADS1292R perform a single conversion when the START pin is taken high or when the START opcode command is sent. As seen in Figure 39, when a conversion is complete, DRDY goes low and further conversions are stopped.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com When using multiple devices, the devices can be synchronized with the START signal. The delay from START to the DRDY signal is fixed for a fixed data rate (see the START subsection of the SPI Interface section for more details on the settling times). Figure 41 shows the behavior of two devices when synchronized with the START signal.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 SPI COMMAND DEFINITIONS The ADS1291, ADS1292, and ADS1292R provide flexible configuration control. The opcode commands summarized in Table 13 control and configure the ADS1291, ADS1292, and ADS1292R operation. The opcode commands are stand-alone, except for the register read and register write operations that require a second command byte plus data.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com START: Start Conversions This opcode starts data conversions. Tie the START pin low to control conversions by command. If conversions are in progress this command has no effect. The STOP opcode command is used to stop conversions. If the START command is immediately followed by a STOP command then have a gap of 4 tCLK cycles between them.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 SDATAC: Stop Read Data Continuous This opcode cancels the Read Data Continuous mode. There is no restriction on the SCLK rate for this command, but the following command must wait for 4 tCLK cycles. RDATA: Read Data Issue this command after DRDY goes low to read the conversion result (in Stop Read Data Continuous mode).
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com RREG: Read From Register This opcode reads register data. The Register Read command is a two-byte opcode followed by the output of the register data. The first byte contains the command opcode and the register address. The second byte of the opcode specifies the number of registers to read – 1. First opcode byte: 001r rrrr, where r rrrr is the starting register address.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 REGISTER MAP Table 14 describes the various ADS1291, ADS1292, and ADS1292R registers. Table 14.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com CONFIG1: Configuration Register 1 Address = 01h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 SINGLE_SHOT 0 0 0 0 DR2 DR1 DR0 This register configures each ADC channel sample rate.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 CONFIG2: Configuration Register 2 Address = 02h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 1 PDB_LOFF_ COMP PDB_REFBUF VREF_4V CLK_EN 0 INT_TEST TEST_FREQ This register configures the test signal, clock, reference, and LOFF buffer. Bit 7 Must be set to '1' Bit 6 PDB_LOFF_COMP: Lead-off comparator power-down This bit powers down the lead-off comparators.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com LOFF: Lead-Off Control Register Address = 03h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 COMP_TH2 COMP_TH1 COMP_TH0 1 ILEAD_OFF1 ILEAD_OFF0 0 FLEAD_OFF This register configures the lead-off detection operation. Bits[7:5] COMP_TH[2:0]: Lead-off comparator threshold These bits determine the lead-off comparator threshold.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 CH1SET: Channel 1 Settings Address = 04h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PD1 GAIN1_2 GAIN1_1 GAIN1_0 MUX1_3 MUX1_2 MUX1_1 MUX1_0 This register configures the power mode, PGA gain, and multiplexer settings channels. See the Input Multiplexer section for details.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com CH2SET: Channel 2 Settings Address = 05h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PD2 GAIN2_2 GAIN2_1 GAIN2_0 MUX2_3 MUX2_2 MUX2_1 MUX2_0 This register configures the power mode, PGA gain, and multiplexer settings channels. See the Input Multiplexer section for details.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 RLD_SENS: Right Leg Drive Sense Selection Address = 06h BIT 7 CHOP1 BIT 6 CHOP0 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PDB_RLD RLD_LOFF_ SENS RLD2N RLD2P RLD1N RLD1P This register controls the selection of the positive and negative signals from each channel for right leg drive derivation. See the Right Leg Drive (RLD DC Bias Circuit) subsection of the ECG-Specific Functions section for details.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com LOFF_SENS: Lead-Off Sense Selection Address = 07h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 FLIP2 FLIP1 LOFF2N LOFF2P LOFF1N LOFF1P This register selects the positive and negative side from each channel for lead-off detection. See the Lead-Off Detection subsection of the ECG-Specific Functions section for details.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 LOFF_STAT: Lead-Off Status Address = 08h BIT 7 0 BIT 6 CLK_DIV BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 RLD_STAT (read only) IN2N_OFF (read only) IN2P_OFF (read only) IN1N_OFF (read only) IN1P_OFF (read only) This register stores the status of whether the positive or negative electrode on each channel is on or off. See the Lead-Off Detection subsection of the ECG-Specific Functions section for details.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com RESP1: Respiration Control Register 1 Address = 09h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESP_ DEMOD_EN1 RESP_MOD_ EN RESP_PH3 RESP_PH2 RESP_PH1 RESP_PH0 1 RESP_CTRL This register controls the respiration functionality. This register applies to the ADS1292R version only. For the ADS1291 and ADS1292 devices, 02h must be written to the RESP1 register.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 RESP2: Respiration Control Register 2 Address = 0Ah BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CALIB_ON 0 0 0 0 RESP_FREQ RLDREF_INT 1 This register controls the respiration and calibration functionality. Bit 7 CALIB_ON: Calibration on This bit is used to enable offset calibration.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com ECG-SPECIFIC FUNCTIONS INPUT MULTIPLEXER (REROUTING THE RIGHT LEG DRIVE SIGNAL) The input multiplexer has ECG-specific functions for the right leg drive signal. The RLD signal is available at the RLDOUT pin once the appropriate channels are selected for RLD derivation, feedback elements are installed external to the chip, and the loop is closed.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 Input Multiplexer (Measuring the Right Leg Drive Signal) The RLDOUT signal can also be routed to a channel (that is not used for the calculation of RLD) for measurement. Figure 48 shows the register settings to route the RLDIN signal to channel 2. The measurement is done with respect to the voltage (AVDD + AVSS) / 2. This feature is useful for debugging purposes during product development.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com LEAD-OFF DETECTION Patient electrode impedances are known to decay over time. It is necessary to continuously monitor these electrode connections to verify a suitable connection is present. The ADS1291, ADS1292, and ADS1292R leadoff detection functional block provides significant flexibility to the user to choose from various lead-off detection strategies.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 DC Lead-Off In this method, the lead-off excitation is with a dc signal. The dc excitation signal can be chosen from either an external pull-up or pull-down resistor or a current source or sink, as shown in Figure 50. One side of the channel is pulled to supply and the other side is pulled to ground. The internal current source and current sink can be swapped by setting the FLIP1 and FLIP2 bits in the LOFF_SENS register.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com RLD Lead-Off The ADS1291, ADS1292, and ADS1292R provide two modes for determining whether the RLD is correctly connected: • RLD lead-off detection during normal operation • RLD lead-off detection during power-up The following sections provide details of the two modes of operation.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 Right Leg Drive (RLD DC Bias Circuit) The right leg drive (RLD) circuitry is used as a means to counter the common-mode interference in a ECG system as a result of power lines and other sources, including fluorescent lights. The RLD circuit senses the common-mode of a selected set of electrodes and creates a negative feedback loop by driving the body with an inverted common-mode signal.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com RLD Configuration with Multiple Devices RLDIN/ RLDREF RLD OUT Power-Down Device N VA1 VA2 RLDINV (AVDD+AVSS) 2 RLDIN/ RLDREF RLD OUT To Input MUX (AVDD+AVSS) 2 To Input MUX To Input MUX Figure 53 shows multiple devices connected to an RLD. Device 2 VA1 VA2 RLDINV RLDIN/ RLDREF (AVDD+AVSS) 2 Device 1 VA1 RLD OUT REXT VA2 RLDINV CEXT Figure 53.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 Internal Respiration Circuitry with Internal Clock (ADS1292R) This mode is set by RESP_CTRL = 0. Figure 54 shows a block diagram of the internal respiration circuitry. The internal modulation and demodulator circuitry can be selectively used. The modulation block is controlled by the RESP_MOD_EN bit and the demodulation block is controlled by the RESP_DEMOD_EN bit.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com Internal Respiration Circuitry with External Clock (ADS1292R) This mode is set by RESP_CTRL = 1. In this mode GPIO1 and GPIO2 are automatically configured as inputs. GPIO1 and GPIO2 cannot be used for other purposes. The signals must be provided as described in Figure 55. (Modulation Clock) GPIO1 tPHASE tBLKDLY (Blocking Signal) GPIO2 Figure 55. Internal Respiration (RESP_CTRL = 1) Timing Diagram Table 16.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 Figure 57 shows a respiration test circuit. Figure 58 and Figure 59 plot noise on channel 1 for the ADS1292R as baseline impedance, gain, and phase are swept. The x-axis is the baseline impedance, normalized to a 30-µA modulation current (as shown in Equation 11). 10 ADS1292R RESP_MODP RBASELINE = 2.21 kW RESP_MODN R2 40.2 kW Channel 1 Noise (µV) IN1P R2 40.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com QUICK-START GUIDE PCB LAYOUT Power Supplies and Grounding The ADS1291, ADS1292, and ADS1292R have two supplies: AVDD and DVDD. AVDD should be as quiet as possible. AVDD provides the supply to the charge pump block and has transients at fCLK. It is important to eliminate noise from AVDD that is non-synchronous with the ADS1291, ADS1292, and ADS1292R operation.
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 Connecting the Device to Bipolar (±1.5 V or 1.8 V) Supplies Figure 61 illustrates the ADS1291, ADS1292, and ADS1292R connected to a bipolar supply. In this example, the analog supplies connect to the device analog supply (AVDD). This supply is referenced to the device analog return (AVSS), and the digital supply (DVDD) is referenced to the device digital ground return (DGND). +1.5 V +1.8 V 1 mF 0.1 mF 0.
ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com POWER-UP SEQUENCING Before device power-up, all digital and analog inputs must be low. At the time of power-up, all of these signals should remain low until the power supplies have stabilized, as shown in Figure 62. At this time, begin supplying the master clock signal to the CLK pin. Wait for time tPOR, then transmit a RESET pulse.
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ADS1291 ADS1292 ADS1292R SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (March 2012) to Revision B Page • Added QFN package to device graphic ................................................................................................................................ 1 • Changed AVSS to DGND row in Absolute Maximum Ratings table .....................
ADS1291 ADS1292 ADS1292R www.ti.com SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012 Changes from Original (December 2011) to Revision A Page • Changed device graphic ....................................................................................................................................................... 1 • Changed device status from Mixed Status to Production Data ............................................................................................
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS1291IPBSR TQFP PBS 32 1000 330.0 16.4 7.2 7.2 1.5 12.0 16.0 Q2 ADS1291IRSMR VQFN RSM 32 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS1291IRSMT VQFN RSM 32 250 180.0 12.4 4.25 4.25 1.15 8.0 12.
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1291IPBSR TQFP PBS 32 1000 367.0 367.0 38.0 ADS1291IRSMR VQFN RSM 32 3000 367.0 367.0 35.0 ADS1291IRSMT VQFN RSM 32 250 210.0 185.0 35.0 ADS1292IPBSR TQFP PBS 32 1000 367.0 367.0 38.0 ADS1292IRSMR VQFN RSM 32 3000 367.0 367.0 35.0 ADS1292IRSMT VQFN RSM 32 250 210.0 185.0 35.
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