ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com Low-Power, 8-Channel, 24-Bit Analog Front-End for Biopotential Measurements Check for Samples: ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R • 23 • • • • • • • • • • • • • • • Eight Low-Noise PGAs and Eight High-Resolution ADCs (ADS1298, ADS1298R) Low Power: 0.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS Minimum/maximum specifications apply for all commercial grade (0°C to +70°C) devices and from –40°C to +85°C for industrial grades devices. Typical specifications are at +25°C. All specifications at DVDD = 1.8V, AVDD – AVSS = 3V (1), VREF = 2.4V, external fCLK = 2.048MHz, data rate = 500SPS, High-Resolution mode, and gain = 6, unless otherwise noted.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum/maximum specifications apply for all commercial grade (0°C to +70°C) devices and from –40°C to +85°C for industrial grades devices. Typical specifications are at +25°C. All specifications at DVDD = 1.8V, AVDD – AVSS = 3V(1), VREF = 2.4V, external fCLK = 2.048MHz, data rate = 500SPS, High-Resolution mode, and gain = 6, unless otherwise noted.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum/maximum specifications apply for all commercial grade (0°C to +70°C) devices and from –40°C to +85°C for industrial grades devices. Typical specifications are at +25°C. All specifications at DVDD = 1.8V, AVDD – AVSS = 3V(1), VREF = 2.4V, external fCLK = 2.048MHz, data rate = 500SPS, High-Resolution mode, and gain = 6, unless otherwise noted.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum/maximum specifications apply for all commercial grade (0°C to +70°C) devices and from –40°C to +85°C for industrial grades devices. Typical specifications are at +25°C. All specifications at DVDD = 1.8V, AVDD – AVSS = 3V(1), VREF = 2.4V, external fCLK = 2.048MHz, data rate = 500SPS, High-Resolution mode, and gain = 6, unless otherwise noted.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum/maximum specifications apply for all commercial grade (0°C to +70°C) devices and from –40°C to +85°C for industrial grades devices. Typical specifications are at +25°C. All specifications at DVDD = 1.8V, AVDD – AVSS = 3V(1), VREF = 2.4V, external fCLK = 2.048MHz, data rate = 500SPS, High-Resolution mode, and gain = 6, unless otherwise noted.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com NOISE MEASUREMENTS NOTE The ADS1294R/6R/8R channel performance differs from the ADS1294/6/8 in regards to respiration circuitry found on channel one. Unless otherwise noted, ADS129x refers to all specifications and functional descriptions of the ADS1294, ADS1296, ADS1298, ADS1294R, ADS1296R, and ADS1298R. The ADS129x noise performance can be optimized by adjusting the data rate and PGA setting.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com Table 3.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com PAG PIN ASSIGNMENTS (continued) NAME PIN FUNCTION DGND 51 Supply CLKSEL 52 Digital input AVSS1 53 Supply Analog ground AVDD1 54 Supply Analog supply VCAP3 55 Analog Analog bypass capacitor; internally generated AVDD + 1.9V.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com TIMING CHARACTERISTICS tCLK CLK tCSSC tSCLK SCLK tCSH tSDECODE CS 1 tSPWL tSPWH 3 2 8 1 tDIHD tDIST tSCCS 3 2 8 tDOHD tDOPD DIN tCSDOZ tCSDOD DOUT Hi-Z Hi-Z NOTE: SPI settings are CPOL = 0 and CPHA = 1. Figure 1.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com TYPICAL CHARACTERISTICS All plots at TA = +25°C, AVDD = 3V, AVSS = 0V, DVDD = 1.8V, internal VREFP = 2.4V, VREFN = AVSS, external clock = 2.048MHz, data rate = 500SPS, High-Resolution mode, and gain = 6, unless otherwise noted. INPUT-REFERRED NOISE NOISE HISTOGRAM 1600 1400 2 1200 1 Occurrences 0 -1 1000 800 600 400 -2 200 Peak-to-Peak Over 10sec = 5mV 9 10 Time (sec) 2.18 0 8 1.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) All plots at TA = +25°C, AVDD = 3V, AVSS = 0V, DVDD = 1.8V, internal VREFP = 2.4V, VREFN = AVSS, external clock = 2.048MHz, data rate = 500SPS, High-Resolution mode, and gain = 6, unless otherwise noted.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) All plots at TA = +25°C, AVDD = 3V, AVSS = 0V, DVDD = 1.8V, internal VREFP = 2.4V, VREFN = AVSS, external clock = 2.048MHz, data rate = 500SPS, High-Resolution mode, and gain = 6, unless otherwise noted.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) All plots at TA = +25°C, AVDD = 3V, AVSS = 0V, DVDD = 1.8V, internal VREFP = 2.4V, VREFN = AVSS, external clock = 2.048MHz, data rate = 500SPS, High-Resolution mode, and gain = 6, unless otherwise noted.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com OVERVIEW NOTE The ADS1294R/6R/8R channel performance differs from the ADS1294/6/8 in regards to respiration circuitry found on channel one. Unless otherwise noted, ADS129x refers to all specifications and functional descriptions of the ADS1294, ADS1296, ADS1298, ADS1294R, ADS1296R, and ADS1298R.
Copyright © 2010–2012, Texas Instruments Incorporated ADS1296/6R/8/8R Product Folder Link(s): ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R WCT IN8N EMI Filter EMI Filter EMI Filter EMI Filter EMI Filter EMI Filter EMI Filter EMI Filter AVSS AVSS1 Internal Respiration Modulator (ADS129xR) MUX WCT From Wmuxb From Wmuxa B A RLD Amplifier PGA8 PGA7 PGA6 PGA5 PGA4 PGA3 PGA2 RLD RLD RLD IN REF OUT From Wmuxc C Power-Supply Signal Lead-Off Excitation Source PGA1 Temperature
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com THEORY OF OPERATION This section discusses the details of the ADS129x internal functional elements. The analog blocks are reviewed first, followed by the digital interface. Blocks implementing ECG-specific functions are covered in the end.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com Device Noise Measurements Setting CHnSET[2:0] = 001 sets the common-mode voltage of (AVDD – AVSS)/2 to both inputs of the channel. This setting can be used to test the inherent noise of the device in the user system. Test Signals (TestP and TestN) Setting CHnSET[2:0] = 101 provides internally-generated test signals for use in sub-system verification at power-up.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com Supply Measurements (MVDDP, MVDDN) Setting CHnSET[2:0] = 011 sets the channel inputs to different supply voltages of the device. For channels 1, 2, 5, 6, 7, and 8, (MVDDP – MVDDN) is [0.5 × (AVDD – AVSS)]; for channel 3 and for channel 4, (MVDDP – MVDDN) is DVDD/4. Note that to avoid saturating the PGA while measuring power supplies, the gain must be set to '1'. For example, if AVDD = 2.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com CM + 1/2VREF +1/2VREF INP CM Voltage -1/2VREF INN = CM Voltage CM - 1/2VREF t Single-Ended Inputs INP CM + 1/2VREF +VREF CM Voltage CM - 1/2VREF INN -VREF t Differential Inputs (INP) + (INN) , Common-Mode Voltage (Single-Ended Mode) = INN. 2 Input Range (Differential Mode) = (AINP - AINN) = VREF - (-VREF) = 2VREF. Common-Mode Voltage (Differential Mode) = Figure 27.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com The resistor string of the PGA that implements the gain has 120kΩ of resistance for a gain of 6. This resistance provides a current path across the outputs of the PGA in the presence of a differential input signal. This current is in addition to the quiescent current specified for the device in the presence of a differential signal at the input.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com DIGITAL DECIMATION FILTER The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for higher data rates. Higher data rates are typically used in ECG applications for implement software PACE detection and ac lead-off detection.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com The sinc filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these frequencies, the filter has infinite attenuation. Figure 30 shows the frequency response of the sinc filter and Figure 31 shows the roll-off of the sinc filter. With a step change at input, the filter takes 3 × tDR to settle.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com REFERENCE Figure 35 shows a simplified block diagram of the internal reference of the ADS129x. The reference voltage is generated with respect to AVSS. When using the internal voltage reference, connect VREFN to AVSS. 22mF VCAP1 R1 (1) Bandgap 2.4V or 4V R3 VREFP (1) 10mF R2 (1) VREFN AVSS To ADC Reference Inputs (1) For VREF = 2.4V: R1 = 12.5kΩ, R2 = 25kΩ, and R3 = 25kΩ.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com CLOCK The ADS129x provide two different methods for device clocking: internal and external. Internal clocking is ideally suited for low-power, battery-powered systems. The internal oscillator is trimmed for accuracy at room temperature. Over the specified temperature range the accuracy varies; see the Electrical Characteristics.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com SPI INTERFACE The SPI-compatible serial interface consists of four signals: CS, SCLK, DIN, and DOUT. The interface reads conversion data, reads and writes registers, and controls the ADS129x operation. The DRDY output is used as a status signal to indicate when data are ready. DRDY goes low when new data are available.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com Data Output (DOUT) The data output pin (DOUT) is used with SCLK to read conversion and register data from the ADS129x. Data on DOUT are shifted out on the rising edge of SCLK. DOUT goes to a high-impedance state when CS is high. In read data continuous mode (see the SPI Command Definitions section for more details), the DOUT output line also indicates when new data are available.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com Figure 38 shows the relationship between DRDY, DOUT, and SCLK during data retrieval (in case of an ADS1298 with a selected data rate that gives 24-bit resolution). DOUT is latched out at the rising edge of SCLK. DRDY is pulled high at the falling edge of SCLK.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com Reset (RESET) There are two methods to reset the ADS129x: pull the RESET pin low, or send the RESET opcode command. When using the RESET pin, take it low to force a reset. Make sure to follow the minimum pulse width timing specifications before taking the RESET pin back high. The RESET command takes effect on the eighth SCLK falling edge of the opcode command.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com Continuous Mode Conversions begin when the START pin is taken high for at least 2 tCLKs or when the START opcode command is sent. As seen in Figure 41, the DRDY output goes high when conversions are started and goes low when data are ready. Conversions continue indefinitely until the START pin is taken low or the STOP opcode command is transmitted.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com Single-Shot Mode The single-shot mode is enabled by setting the SINGLE_SHOT bit in CONFIG4 register to '1'. In single-shot mode, the ADS129x perform a single conversion when the START pin is taken high or when the START opcode command is sent. As seen in Figure 42, when a conversion is complete, DRDY goes low and further conversions are stopped.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com When using multiple devices, the devices can be synchronized with the START signal. The delay from START to the DRDY signal is fixed for a fixed data rate (see the START subsection of the SPI Interface section for more details on the settling times). Figure 44 shows the behavior of two devices when synchronized with the START signal as an example.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com Cascaded Mode Figure 45a shows a configuration with two devices cascaded together. One of the devices is an ADS1298 (eight channels) and the other is an ADS1294 (four channels). Together, they create a system with 12 channels. DOUT, SCLK, and DIN are shared. Each device has its own chip select.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com In a case where all devices in the chain operate in the same register setting, DIN can be shared as well and thereby reduce the SPI communication signals to four, regardless of the number of devices. However, because the individual devices cannot be programmed, the RLD driver cannot be shared among the multiple devices. Furthermore, an external clock must be used.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com SPI COMMAND DEFINITIONS The ADS129x provide flexible configuration control. The opcode commands, summarized in Table 11, control and configure the operation of the ADS129x. The opcode commands are stand-alone, except for the register read and register write operations that require a second command byte plus data.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com START: Start Conversions This opcode starts data conversions. Tie the START pin low to control conversions by command. If conversions are in progress this command has no effect. The STOP opcode command is used to stop conversions. If the START command is immediately followed by a STOP command, there must be a gap of 4 tCLK cycles between the two commands.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com RDATA: Read Data Issue this command after DRDY goes low to read the conversion result (in Stop Read Data Continuous mode). There is no restriction on the SCLK rate for this command, and there is no wait time needed for the subsequent commands or data retrieval SCLKs.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com RREG: Read From Register This opcode reads register data. The Register Read command is a two-byte opcode followed by the output of the register data. The first byte contains the command opcode and the register address. The second byte of the opcode specifies the number of registers to read – 1. First opcode byte: 001r rrrr, where r rrrr is the starting register address.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com REGISTER MAP Table 12 lists the various ADS129x registers. Table 12.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com User Register Description ID: ID Control Register (Factory-Programmed, Read-Only) Address = 00h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DEV_ID7 DEV_ID6 DEV_ID5 1 0 DEV_ID2 DEV_ID1 DEV_ID0 The ID Control Register is programmed during device manufacture to indicate device characteristics.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com CONFIG1: Configuration Register 1 Address = 01h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 HR DAISY_EN CLK_EN 0 0 DR2 DR1 DR0 Bit 7 HR: High-Resolution/Low-Power mode This bit determines whether the device runs in Low-Power or High-Resolution mode.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com CONFIG2: Configuration Register 2 Address = 02h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 WCT_CHOP INT_TEST 0 TEST_AMP TEST_FREQ1 TEST_FREQ0 Configuration Register 2 configures the test signal generation. See the Input Multiplexer section for more details.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com CONFIG3: Configuration Register 3 Address = 03h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PD_REFBUF 1 VREF_4V RLD_MEAS RLDREF_INT PD_RLD RLD_LOFF_SENS RLD_STAT Configuration Register 3 configures multi-reference and RLD operation. Bit 7 PD_REFBUF: Power-down reference buffer This bit determines the power-down reference buffer state.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com LOFF: Lead-Off Control Register Address = 04h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 COMP_TH2 COMP_TH1 COMP_TH0 VLEAD_OFF_EN ILEAD_OFF1 ILEAD_OFF0 FLEAD_OFF1 FLEAD_OFF0 The Lead-Off Control Register configures the Lead-Off detection operation. Bits[7:5] COMP_TH[2:0]: Lead-off comparator threshold These bits determine the lead-off comparator threshold level setting.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com CHnSET: Individual Channel Settings (n = 1 : 8) Address = 05h to 0Ch BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PD GAIN2 GAIN1 GAIN0 0 MUXn2 MUXn1 MUXn0 The CH[1:8]SET Control Register configures the power mode, PGA gain, and multiplexer settings channels. See the Input Multiplexer section for details.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com LOFF_SENSP Address = 0Fh BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 LOFF8P LOFF7P LOFF6P LOFF5P LOFF4P LOFF3P LOFF2P LOFF1P This register selects the positive side from each channel for lead-off detection. See the Lead-Off Detection subsection of the ECG-Specific Functions section for details.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com LOFF_STATN (Read-Only Register) Address = 13h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 IN8N_OFF IN7N_OFF IN6N_OFF IN5N_OFF IN4N_OFF IN3N_OFF IN2N_OFF IN1N_OFF This register stores the status of whether the negative electrode on each channel is on or off. See the Lead-Off Detection subsection of the ECG-Specific Functions section for details.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com RESP: Respiration Control Register Address = 16h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESP_ DEMOD_EN1 RESP_MOD_ EN1 1 RESP_PH2 RESP_PH1 RESP_PH0 RESP_CTRL1 RESP_CTRL0 This register provides the controls for the respiration circuitry; see the Respiration section for details.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com CONFIG4: Configuration Register 4 Address = 17h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESP_FREQ2 RESP_FREQ1 RESP_FREQ0 0 SINGLE_SHOT WCT_TO_RLD PD_LOFF_COMP 0 Bits[7:5] RESP_FREQ[2:0]: Respiration modulation frequency These bits control the respiration control frequency when RESP_CTRL[1:0] = 10 or RESP_CTRL[1:0] = 10 (1).
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com WCT1: Wilson Central Terminal and Augmented Lead Control Register Address = 18h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 aVF_CH6 aVL_CH5 aVR_CH7 aVR_CH4 PD_WCTA WCTA2 WCTA1 WCTA0 The WCT1 control register configures the device WCT circuit channel selection and the augmented leads.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com WCT2: Wilson Central Terminal Control Register Address = 19h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PD_WCTC PD_WCTB WCTB2 WCTB1 WCTB0 WCTC2 WCTC1 WCTC0 The WCT2 configuration register configures the device WCT circuit channel selection.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com ECG-SPECIFIC FUNCTIONS INPUT MULTIPLEXER (REROUTING THE RIGHT LEG DRIVE SIGNAL) The input multiplexer has ECG-specific functions for the right leg drive signal. The RLD signal is available at the RLDOUT pin once the appropriate channels are selected for the RLD derivation, feedback elements are installed external to the chip, and the loop is closed.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com INPUT MULTIPLEXER (MEASURING THE RIGHT LEG DRIVE SIGNAL) Also, the RLDOUT signal can be routed to a channel (that is not used for the calculation of RLD) for measurement. Figure 52 shows the register settings to route the RLDIN signal to channel 8. The measurement is done with respect to the voltage on the RLDREF pin. If RLDREF is chosen to be internal, it would be at (AVDD + AVSS)/2.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com WILSON CENTRAL TERMINAL (WCT) AND CHEST LEADS In the standard 12-lead ECG, WCT voltage is defined as the average of Right Arm (RA), Left Arm (LA), and Left Leg (LL) electrodes. This voltage is used as the reference voltage for the measurement of the chest leads. The ADS129x has three integrated low-noise amplifiers that generate the WCT voltage.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com As mentioned previously in this section, all three WCT amplifiers can be connected to one of eight analog input pins. The inputs of the amplifiers are chopped and the chopping frequency varies with the data rates of the ADS129x. The chop frequency for the three highest data rates scale 1:1. For example, at 32kSPS data rate, the chop frequency is 32kHz in HR mode with WCT_CHOP = 0.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com Augmented Leads In the typical implementation of the 12-lead ECG with eight channels, the augmented leads are calculated digitally. In certain applications, it may be required that all leads be derived in analog rather than digital. The ADS1298/8R provides the option to generate the augmented leads by routing appropriate averages to channels 5 to 7.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com LEAD-OFF DETECTION Patient electrode impedances are known to decay over time. It is necessary to continuously monitor these electrode connections to verify a suitable connection is present. The ADS129x lead-off detection functional block provides significant flexibility to the user to choose from various lead-off detection strategies.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com AC Lead-Off This method uses an out-of-band ac signal for excitation. The ac signal is generated by alternatively providing pull-up resistors and pull-down resistors at the input with a fixed frequency. The ac signal is passed through an anti-aliasing filter to avoid aliasing. The frequency can be chosen by the FLEAD_OFF[1:0] bits in the LOFF register.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com RLD LEAD-OFF The ADS129x provide two modes for determining whether the RLD is correctly connected: • RLD lead-off detection during normal operation • RLD lead-off detection during power-up The following sections provide details of the two modes of operation.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com RIGHT LEG DRIVE (RLD DC BIAS CIRCUIT) The right leg drive (RLD) circuitry is used as a means to counter the common-mode interference in a ECG system as a result of power lines and other sources, including fluorescent lights. The RLD circuit senses the common-mode of a selected set of electrodes and creates a negative feedback loop by driving the body with an inverted common-mode signal.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 From MUX1P www.ti.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com WCT as RLD In certain applications, the right leg drive is derived as the average of RA, LA, and LL. This level is the same as the WCT voltage. The WCT amplifier has limited drive strength and thus should be used only to drive very high impedances directly. The ADS129x provide an option to internally buffer the WCT signal by setting the WCT_TO_RLD bit in the CONFIG4 register.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com PACE DETECT The ADS129x provide flexibility for PACE detection either in software or by external hardware. The software approach is made possible by providing sampling rates up to 32kSPS. The external hardware approach is made possible by bringing out the output of the PGA at two pins: TESTP_PACE_OUT1 and TESTN_PACE_OUT2.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com RESPIRATION The ADS1294R/6R/8R provide three modes for respiration impedance measurement: external respiration, internal respiration using on-chip modulation signals, and internal respiration using user-generated modulation signals, as shown in Table 14. Table 14. Respiration Control RESP.RESP_CTRL[1] RESP.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com External Respiration Circuitry Option (RESP_CTRL = 01b) In this mode, GPIO2, GPIO3, and GPIO4 are automatically configured as outputs. The phase relationship between the signals is shown in Figure 65. GPIO2 is the exclusive-OR of GPIO3 and GPIO4, as shown in Figure 66. GPIO3 is the modulation signal, and GPIO4 is the de-modulation signal.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com Internal Respiration Circuitry with Internal Clock (RESP_CTRL = 10b, ADS1294R/6R/8R Only) Figure 67 shows a block diagram of the internal respiration circuitry. The internal modulation and demodulator circuitry can be selectively used. The modulation block is controlled by the RESP_MOD_EN bit and the demodulation block is controlled by the RESP_DEMOD_EN bit.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com Internal Respiration Circuitry with User-Generated Signals (RESP_CTRL = 11b, ADS1294R/6R/8R Only) In this mode GPIO2, GPIO3, and GPIO4 are automatically configured as inputs. GPIO2, GPIO3, and GPIO4 cannot be used for other purposes. The signals must be provided as described in Figure 68. The internal master clock is not recommended in this mode.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com Figure 70 shows a respiration test circuit. Figure 71 and Figure 72 plot noise on channel 1 for the ADS1294R/6R/8R as baseline impedance, gain, and phase are swept. The x-axis is the baseline impedance, normalized to a 29µA modulation current (as shown in Equation 8). 10 ADS1294R/6R/8R 9.5 Channel 1 Noise (mVPP) IN1P R2 40.2kW RESP_MODP RBASELINE = 2.21kW RESP_MODN R2 40.2kW 9 Phase = 112.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com QUICK-START GUIDE PCB LAYOUT Power Supplies and Grounding The ADS129x have three supplies: AVDD, AVDD1, and DVDD. Both AVDD and AVDD1 should be as quiet as possible. AVDD1 provides the supply to the charge pump block and has transients at fCLK. Therefore, it is recommended that AVDD1 and AVSS1 be star-connected to AVDD and AVSS.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com Connecting the Device to Bipolar (±1.5V/1.8V) Supplies Figure 74 illustrates the ADS129x connected to a bipolar supply. In this example, the analog supplies connect to the device analog supply (AVDD). This supply is referenced to the device analog return (AVSS), and the digital supply (DVDD) is referenced to the device digital ground return (DGND). +1.5V +1.8V 1mF 0.1mF 0.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com POWER-UP SEQUENCING Before device power-up, all digital and analog inputs must be low. At the time of power-up, all of these signals should remain low until the power supplies have stabilized, as shown in Figure 76. At this time, begin supplying the master clock signal to the CLK pin. Wait for time tPOR, then transmit a RESET pulse.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com Analog/Digital Power-Up Set CLKSEL Pin = 0 and Provide External Clock fCLK = 2.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (October 2011) to Revision I Page • Added eighth Features bullet (list of standards supported) ..................................................................................................
ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R SBAS459I – JANUARY 2010 – REVISED JANUARY 2012 www.ti.com Changes from Revision G (February 2011) to Revision H Page • Deleted Non-Magnetic BGA Package Features bullet ......................................................................................................... 1 • Added (ADS1298) to High-Resolution mode and Low-Power mode subsection headers of Supply Current section in Electrical Characteristics table .................................
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com Orderable Device ADS1298RIZXGT 23-Nov-2011 Status (1) ACTIVE Package Type Package Drawing NFBGA ZXG Pins 64 Package Qty 250 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish SNAGCU MSL Peak Temp (3) Samples (Requires Login) Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS1294CZXGR NFBGA ZXG 64 ADS1294CZXGT ADS1294IPAGR NFBGA ZXG TQFP PAG ADS1294RIZXGR NFBGA ADS1294RIZXGT SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.3 2.25 12.0 16.0 Q1 1000 330.0 16.4 64 250 330.0 16.4 8.3 8.3 2.25 12.0 16.0 Q1 64 1500 330.0 24.4 13.0 13.0 1.5 16.0 24.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1294CZXGR NFBGA ZXG 64 1000 336.6 336.6 28.6 ADS1294CZXGT NFBGA ZXG 64 250 336.6 336.6 28.6 ADS1294IPAGR TQFP PAG 64 1500 367.0 367.0 45.0 ADS1294RIZXGR NFBGA ZXG 64 1000 336.6 336.6 28.6 ADS1294RIZXGT NFBGA ZXG 64 250 336.6 336.6 28.6 ADS1296CZXGR NFBGA ZXG 64 1000 336.6 336.6 28.
MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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