ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 Low-Noise, 8-Channel, 24-Bit Analog Front-End for Biopotential Measurements Check for Samples: ADS1299 FEATURES 1 • 23 • • • • • • • • The ADS1299 has a flexible input multiplexer per channel that can be independently connected to the internally-generated signals for test, temperature, and lead-off detection. Additionally, any configuration of input channels can be selected for derivation of the patient bias output signal.
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS Minimum and maximum specifications apply from –40°C to +85°C. Typical specifications are at +25°C. All specifications are at DVDD = 3.3 V, AVDD – AVSS = 5 V, VREF = 4.5 V, external fCLK = 2.048 MHz, data rate = 250 SPS, and gain = 12, unless otherwise noted.
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum and maximum specifications apply from –40°C to +85°C. Typical specifications are at +25°C. All specifications are at DVDD = 3.3 V, AVDD – AVSS = 5 V, VREF = 4.5 V, external fCLK = 2.048 MHz, data rate = 250 SPS, and gain = 12, unless otherwise noted.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS (continued) Minimum and maximum specifications apply from –40°C to +85°C. Typical specifications are at +25°C. All specifications are at DVDD = 3.3 V, AVDD – AVSS = 5 V, VREF = 4.5 V, external fCLK = 2.048 MHz, data rate = 250 SPS, and gain = 12, unless otherwise noted. ADS1299 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CLOCK Internal oscillator clock frequency Nominal frequency Internal clock accuracy 2.
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com PARAMETRIC MEASUREMENT INFORMATION NOISE MEASUREMENTS The ADS1299 noise performance can be optimized by adjusting the data rate and PGA setting. When averaging is increased by reducing the data rate, the noise drops correspondingly. Increasing the PGA value reduces the input-referred noise, which is particularly useful when measuring low-level biopotential signals.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 Table 3. Input-Referred Noise (μVRMS / μVPP) in Normal Mode 5-V Analog Supply and 4.5-V Reference (1) PGA GAIN = 8 PGA GAIN = 12 DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) μVRMS μVPP SNR (dB) NOISEFREE BITS ENOB μVRMS μVPP SNR (dB) NOISEFREE BITS ENOB 000 16000 4193 3.05 21.32 102.3 15.69 16.99 2.27 15.89 101.3 15.53 16.83 001 8000 2096 1.11 7.80 111.0 17.14 18.45 0.92 6.41 109.
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com TIMING CHARACTERISTICS tCLK CLK tCSSC tSCLK SCLK tCSH tSDECODE CS 1 tSPWL tSPWH 3 2 8 1 3 2 tDIHD tDIST tSCCS 8 tDOHD tDOPD DIN tCSDOZ tCSDOD Hi-Z Hi-Z DOUT NOTE: SPI settings are CPOL = 0 and CPHA = 1. Figure 1. Serial Interface Timing tDISCK2ST MSBD1 DAISY_IN SCLK DOUT 1 tDISCK2HT LSBD1 3 2 216 219 MSBD1 LSB MSB 218 217 Figure 2.
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ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS All plots are at TA = +25°C, AVDD = 5 V, AVSS = 0 V, DVDD = 3.3 V, internal VREFP = 4.5 V, VREFN = AVSS, external clock = 2.048 MHz, data rate = 250 SPS, and gain = 12, unless otherwise noted. INPUT-REFERRED NOISE NOISE HISTOGRAM 0.5 800 Gain = 24 Gain = 24 700 0.3 600 0.2 Occurences 0.1 0 −0.1 500 400 300 −0.2 200 −0.3 100 −0.4 G003 0.5 0 10 0.4 9 0.3 8 0.2 7 0.1 5 6 Time (s) 0 4 −0.1 3 −0.
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) All plots are at TA = +25°C, AVDD = 5 V, AVSS = 0 V, DVDD = 3.3 V, internal VREFP = 4.5 V, VREFN = AVSS, external clock = 2.048 MHz, data rate = 250 SPS, and gain = 12, unless otherwise noted. THD vs FREQUENCY INL vs PGA GAIN 12 Gain = 1 Gain = 2 Gain = 4 Gain = 6 Gain = 8 Gain = 12 Gain = 24 −65 −70 −75 −80 Data Rate = 8 kSPS AIN = −0.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) All plots are at TA = +25°C, AVDD = 5 V, AVSS = 0 V, DVDD = 3.3 V, internal VREFP = 4.5 V, VREFN = AVSS, external clock = 2.048 MHz, data rate = 250 SPS, and gain = 12, unless otherwise noted.
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com OVERVIEW The ADS1299 is a low-noise, low-power, multichannel, simultaneously-sampling, 24-bit, delta-sigma (ΔΣ) analogto-digital converter (ADC) with an integrated programmable gain amplifier (PGA). This device integrates various EEG-specific functions that makes it well-suited for scalable electroencephalography (EEG) applications.
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ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com THEORY OF OPERATION This section contains details of the ADS1299 internal functional elements. The analog blocks are discussed first, followed by the digital interface. Blocks implementing EEG-specific functions are covered at the end of this document.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 Device Noise Measurements Setting CHnSET[2:0] = 001 sets the common-mode voltage of [(VREFP + VREFN) / 2] to both channel inputs. This setting can be used to test inherent device noise in the user system. Test Signals (TestP and TestN) Setting CHnSET[2:0] = 101 provides internally-generated test signals for use in sub-system verification at powerup. This functionality allows the device internal signal chain to be tested out.
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com Auxiliary Single-Ended Input The BIASIN pin is primarily used for routing the bias signal to any electrodes in case the bias electrode falls off. However, the BIASIN pin can be used as a multiple single-ended input channel. The signal at the BIASIN pin can be measured with respect to the voltage at the BIASREF pin using any of the eight channels.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 PGA SETTINGS AND INPUT RANGE The low-noise PGA is a differential input and output amplifier, as shown in Figure 23. The PGA has seven gain settings (1, 2, 4, 6, 8, 12, and 24) that can be set by writing to the CHnSET register (see the CHnSET: Individual Channel Settings subsection of the Register Map section for details). The ADS1299 has CMOS inputs and therefore has negligible current noise.
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com Input Common-Mode Range The usable input common-mode range of the front-end depends on various parameters, including the maximum differential input signal, supply voltage, PGA gain, and so forth. This range is described in Equation 2: AVDD - 0.2 - Gain VMAX_DIFF 2 > CM > AVSS + 0.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 DIGITAL DECIMATION FILTER The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for higher data rates. Higher data rates are typically used in EEG applications for ac lead-off detection. The digital filter on each channel consists of a third-order sinc filter.
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com 0 0 -20 -0.5 -40 -1 Gain (dB) Gain (dB) The sinc filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these frequencies, the filter has infinite attenuation. Figure 25 shows the sinc filter frequency response and Figure 26 shows the sinc filter roll-off. With a step change at input, the filter takes 3 × tDR to settle.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 0 −20 Gain (dB) −40 −60 −80 −100 −120 −140 0 0.5 1 1.5 2 2.5 3 Normalized Frequency (fIN/fMOD) 3.5 4 G029 Figure 29. Transfer Function of On-Chip Decimation Filters Until 4 fMOD for DR[2:0] = 000 and DR[2:0] = 110 REFERENCE Figure 30 shows a simplified block diagram of the ADS1299 internal reference. The 4.5-V reference voltage is generated with respect to AVSS. When using the internal voltage reference, connect VREFN to AVSS.
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com 100 kW 10 pF +5 V 0.1 mF 100 W +5 V VIN 10 mF OUT 22 mF REF5025 TRIM To VREFP Pin OPA211 100 W 0.1 mF 100 mF 22 mF Figure 31.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 CLOCK The ADS1299 provides two methods for device clocking: internal and external. Internal clocking is ideally suited for low-power, battery-powered systems. The internal oscillator is trimmed for accuracy at room temperature. Accuracy varies over the specified temperature range; see the Electrical Characteristics. Clock selection is controlled by the CLKSEL pin and the CLK_EN register bit.
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com SPI INTERFACE The SPI-compatible serial interface consists of four signals: CS, SCLK, DIN, and DOUT. The interface reads conversion data, reads and writes registers, and controls ADS1299 operation. The DRDY output is used as a status signal to indicate when data are ready. DRDY goes low when new data are available. Chip Select (CS) Chip select (CS) selects the ADS1299 for SPI communication.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 Data Output (DOUT) The data output pin (DOUT) is used with SCLK to read conversion and register data from the ADS1299. Data on DOUT are shifted out on the SCLK rising edge. DOUT goes to a high-impedance state when CS is high. In read data continuous mode (see the SPI Command Definitions section for more details), the DOUT output line also indicates when new data are available.
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com Figure 33 shows the relationship between DRDY, DOUT, and SCLK during data retrieval (in case of an ADS1299 with a selected data rate that gives 24-bit resolution). DOUT is latched out at the SCLK rising edge. DRDY is pulled high at the SCLK falling edge. Note that DRDY goes high on the first SCLK falling edge, regardless of whether data are being retrieved from the device or a command is being sent through the DIN pin.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 Reset (RESET) There are two methods to reset the ADS1299: pull the RESET pin low, or send the RESET opcode command. When using the RESET pin, take the pin low to force a reset. Make sure to follow the minimum pulse width timing specifications before taking the RESET pin back high. The RESET command takes effect on the eighth SCLK falling edge of the opcode command.
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com Continuous Mode Conversions begin when the START pin is taken high or when the START opcode command is sent. As seen in Figure 36, the DRDY output goes high when conversions are started and goes low when data are ready. Conversions continue indefinitely until the START pin is taken low or the STOP opcode command is transmitted. When the START pin is pulled low or the stop command is issued, the conversion in progress is allowed to complete.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 Single-Shot Mode Single-shot mode is enabled by setting the SINGLE_SHOT bit in the CONFIG4 register to '1'. In single-shot mode, the ADS1299 performs a single conversion when the START pin is taken high or when the START opcode command is sent. As seen in Figure 38, when a conversion is complete, DRDY goes low and further conversions are stopped. Regardless of whether the conversion data are read or not, DRDY remains low.
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com When using multiple devices, the devices can be synchronized with the START signal. The delay from START to the DRDY signal is fixed for a fixed data rate (see the START subsection of the SPI Interface section for more details on the settling times). Figure 39 shows the behavior of two devices when synchronized with the START signal.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 Standard Mode Figure 40a shows a configuration with two devices cascaded together. Together, the devices create a system with 16 channels. DOUT, SCLK, and DIN are shared. Each device has its own chip select. When a device is not selected by the corresponding CS being driven to logic 1, the DOUT of this device is high-impedance. This structure allows the other device to take control of the DOUT bus.
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com When all devices in the chain operate in the same register setting, DIN can be shared as well. This configuration reduces the SPI communication signals to four, regardless of the number of devices. However, because the individual devices cannot be programmed, the BIAS driver cannot be shared among the multiple devices. Furthermore, an external clock must be used.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 SPI COMMAND DEFINITIONS The ADS1299 provides flexible configuration control. The opcode commands, summarized in Table 10, control and configure device operation. The opcode commands are stand-alone, except for the register read and write operations that require a second command byte plus data. CS can be taken high or held low between opcode commands but must stay low for the entire command operation (especially for multi-byte commands).
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com STOP: Stop Conversions This opcode stops conversions. Tie the START pin low to control conversions by command. When the STOP command is sent, the conversion in progress completes and further conversions are stopped. If conversions are already stopped, this command has no effect. There are no SCLK rate restrictions for this command and it can be issued at any time.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 SDATAC: Stop Read Data Continuous This opcode cancels the Read Data Continuous mode. There are no SCLK rate restrictions for this command, but the next command must wait for 4 tCLK cycles. RDATA: Read Data Issue this command after DRDY goes low to read the conversion result (in Stop Read Data Continuous mode).
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com RREG: Read From Register This opcode reads register data. The Register Read command is a two-byte opcode followed by the register data output. The first byte contains the command opcode and register address. The second opcode byte specifies the number of registers to read – 1. First opcode byte: 001r rrrr, where r rrrr is the starting register address. Second opcode byte: 000n nnnn, where n nnnn is the number of registers to read – 1.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 REGISTER MAP Table 11 describes the various ADS1299 registers. Table 11.
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com User Register Description ID: ID Control Register (Factory-Programmed, Read-Only) Address = 00h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REV_ID3 REV_ID2 REV_ID1 1 DEV_ID2 DEV_ID1 NU_CH2 NU_CH1 This register is programmed during device manufacture to indicate device characteristics.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 CONFIG2: Configuration Register 2 Address = 02h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 1 1 0 INT_CAL 0 CAL_AMP0 CAL_FREQ1 CAL_FREQ0 This register configures the test signal generation. See the Input Multiplexer section for more details. Bits[7:5] Must always be set to '110' Bit 4 INT_CAL: TEST source This bit determines the source for the Test signal.
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com CONFIG3: Configuration Register 3 Address = 03h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PD_REFBUF 1 1 BIAS_MEAS BIASREF_INT PD_BIAS BIAS_LOFF_SENS BIAS_STAT This register configures multi-reference and bias operations. Bit 7 PD_REFBUF: Power-down reference buffer This bit determines the power-down reference buffer state.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 LOFF: Lead-Off Control Register Address = 04h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 COMP_TH2 COMP_TH1 COMP_TH0 0 ILEAD_OFF1 ILEAD_OFF0 FLEAD_OFF1 FLEAD_OFF0 This register configures the lead-off detection operation. Bits[7:5] COMP_TH[2:0]: Lead-off comparator threshold These bits determine the lead-off comparator threshold level setting.
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com CHnSET: Individual Channel Settings (n = 1:8) Address = 05h to 0Ch BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PD1 GAIN12 GAIN11 GAIN10 SRB2 MUX12 MUX11 MUX10 This register configures the power mode, PGA gain, and multiplexer settings channels. See the Input Multiplexer section for details. CH[2:8]SET are similar to CH1SET, corresponding to the respective channels.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 LOFF_SENSP: Lead Off Positive Sense Selection Address = 0Fh BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 LOFFP8 LOFFP7 LOFFP6 LOFFP5 LOFFP4 LOFFP3 LOFFP2 LOFFP1 This register selects the positive side from each channel for lead-off detection. See the Lead-Off Detection subsection of the EEG-Specific Functions section for details.
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com GPIO: General-Purpose I/O Register Address = 14h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 GPIOD4 GPIOD3 GPIOD2 GPIOD1 GPIOC4 GPIOC3 GPIOC2 GPIOC1 This register controls the action of the four GPIO pins. Bits[7:4] GPIOD[4:1]: GPIO data These bits are used to read and write data to the GPIO ports.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 CONFIG4: Configuration Register 4 Address = 17h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 0 0 SINGLE_SHOT 0 PD_LOFF_COMP 0 Bits[7:4] Must always be set to '0' Bit 3 SINGLE_SHOT: Single-shot conversion This bit sets the conversion mode.
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com EEG-SPECIFIC FUNCTIONS INPUT MULTIPLEXER (Rerouting the BIAS Drive Signal) The input multiplexer has EEG-specific functions for the bias drive signal. The BIAS signal is available at the BIASOUT pin when the appropriate channels are selected for BIAS derivation, feedback elements are installed external to the chip, and the loop is closed. This signal can either be fed after filtering or fed directly into the BIASIN pin, as shown in Figure 46.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 INPUT MULTIPLEXER (Measuring the BIAS Drive Signal) Also, the BIASOUT signal can be routed to a channel (that is not used for the calculation of BIAS) for measurement. Figure 47 shows the register settings to route the BIASIN signal to channel 8. The measurement is done with respect to the voltage on the BIASREF pin. If BIASREF is chosen to be internal, it would be at [(AVDD + AVSS) / 2].
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com LEAD-OFF DETECTION Patient electrode impedances are known to decay over time. These electrode connections must be continuously monitored to verify that a suitable connection is present. The ADS1299 lead-off detection functional block provides significant flexibility to the user to choose from various lead-off detection strategies. Though called leadoff detection, this is in fact an electrode-off detection.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 DC Lead-Off In this method, the lead-off excitation is with a dc signal. The dc excitation signal can be chosen from either an external pull-up or pull-down resistor or an internal current source or sink, as shown in Figure 49. One side of the channel is pulled to supply and the other side is pulled to ground. The pull-up and pull-down current can be swapped (as shown in Figure 49b and Figure 49c) by setting the bits in the LOFF_FLIP register.
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com BIAS LEAD-OFF The ADS1299 provides two modes for determining whether the BIAS is correctly connected: • BIAS lead-off detection during normal operation • BIAS lead-off detection during power-up The following sections provide details of the two modes of operation.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 BIAS DRIVE (DC BIAS CIRCUIT) The bias circuitry is used as a means to counter the common-mode interference in a EEG system as a result of power lines and other sources, including fluorescent lights. The bias circuit senses the common-mode of a selected set of electrodes and creates a negative feedback loop by driving the body with an inverted commonmode signal.
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com From MUX1P BIAS1P 220 kW PGA1P 18.15 kW 220 kW From MUX2P BIAS2P PGA2P 3.3 kW 18.15 kW 18.15 kW 3.3 kW 220 kW PGA1N From MUX1N BIAS1N From MUX3P BIAS3P 18.15 kW 220 kW PGA2N From MUX2N BIAS2N 220 kW PGA3P 18.15 kW 220 kW From MUX4P BIAS4P PGA4P 3.3 kW 18.15 kW 18.15 kW 3.3 kW 220 kW PGA3N From MUX3N BIAS3N From MUX5P BIAS5P 18.15 kW 220 kW PGA4N BIAS4N From MUX4N BIAS6P From MUX6P 220 kW PGA5P 18.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 QUICK-START GUIDE PCB LAYOUT Power Supplies and Grounding The ADS1299 has three supplies: AVDD, AVDD1, and DVDD. Both AVDD and AVDD1 should be as quiet as possible. AVDD1 provides the supply to the charge pump block and has transients at fCLK. Therefore, AVDD1 and AVSS1 are recommended to be star-connected to AVDD and AVSS. It is important to eliminate noise from AVDD and AVDD1 that is non-synchronous with the ADS1299 operation.
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com Connecting the Device to Bipolar (±2.5 V and 3.3 V) Supplies Figure 54 illustrates the ADS1299 connected to a bipolar supply. In this example, the analog supplies connect to the device analog supply (AVDD). This supply is referenced to the device analog return (AVSS), and the digital supply (DVDD) is referenced to the device digital ground return (DGND). +2.5 V +3.3 V 1 mF 0.1 mF 0.1 mF 1 mF AVDD AVDD1 DVDD VREFP VREFN 0.1 mF 10 mF -2.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 POWER-UP SEQUENCING Before device power-up, all digital and analog inputs must be low. At the time of power-up, all of these signals should remain low until the power supplies have stabilized, as shown in Figure 55. At this time, begin supplying the master clock signal to the CLK pin. Wait for time tPOR, then transmit a RESET pulse.
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com Analog and Digital Power-Up Set CLKSEL Pin = 0 and Provide External Clock fCLK = 2.
ADS1299 www.ti.com SBAS499A – JULY 2012 – REVISED AUGUST 2012 Lead-Off Sample code to set dc lead-off with pull-up and pull-down resistors on all channels.
ADS1299 SBAS499A – JULY 2012 – REVISED AUGUST 2012 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (July 2012) to Revision A • 60 Page Changed product column of Family and Ordering Information table ....................................................................................
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE MATERIALS INFORMATION www.ti.com 8-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS1299IPAGR Package Package Pins Type Drawing TQFP PAG 64 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1500 330.0 24.4 Pack Materials-Page 1 13.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.0 1.5 16.0 24.
PACKAGE MATERIALS INFORMATION www.ti.com 8-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1299IPAGR TQFP PAG 64 1500 367.0 367.0 45.
MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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