ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561A – JUNE 2012 – REVISED APRIL 2013 Analog Front-End for Power Monitoring, Control, and Protection Check for Samples: ADS131E04, ADS131E06 , ADS131E08 FEATURES 1 • • 23 • • • • • • • • Eight Differential Current and Voltage Inputs Outstanding Performance: – Exceeds Class 0.1 Performance – Dynamic Range at 1 kSPS: 118 dB – Crosstalk: –110 dB – THD: –90 dB at 50 Hz and 60 Hz Supply Range: – Analog: – +3 V to +5 V (Unipolar) – ±2.
ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561A – JUNE 2012 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS Minimum and maximum specifications apply from –40°C to +105°C. Typical specifications are at +25°C. All specifications are at DVDD = 1.8 V, AVDD = 3 V, AVSS = 0 V, VREF = 2.4 V, external fCLK = 2.048 MHz, data rate = 8 kSPS, and gain = 1, unless otherwise noted.
ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum and maximum specifications apply from –40°C to +105°C. Typical specifications are at +25°C. All specifications are at DVDD = 1.8 V, AVDD = 3 V, AVSS = 0 V, VREF = 2.4 V, external fCLK = 2.048 MHz, data rate = 8 kSPS, and gain = 1, unless otherwise noted. ADS131E0x PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPERATIONAL AMPLIFIER Integrated noise 0.
ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561A – JUNE 2012 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS (continued) Minimum and maximum specifications apply from –40°C to +105°C. Typical specifications are at +25°C. All specifications are at DVDD = 1.8 V, AVDD = 3 V, AVSS = 0 V, VREF = 2.4 V, external fCLK = 2.048 MHz, data rate = 8 kSPS, and gain = 1, unless otherwise noted. ADS131E0x PARAMETER TEST CONDITIONS MIN AVDD – DVDD –2.
ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum and maximum specifications apply from –40°C to +105°C. Typical specifications are at +25°C. All specifications are at DVDD = 1.8 V, AVDD = 3 V, AVSS = 0 V, VREF = 2.4 V, external fCLK = 2.048 MHz, data rate = 8 kSPS, and gain = 1, unless otherwise noted.
ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561A – JUNE 2012 – REVISED APRIL 2013 PARAMETER MEASUREMENT INFORMATION NOISE MEASUREMENTS The ADS131E0x noise performance can be optimized by adjusting the data rate and PGA setting. As the averaging is increased by reducing the data rate, the noise drops correspondingly. Increasing the PGA value reduces the input-referred noise, which is particularly useful when measuring low-level signals.
ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com TIMING CHARACTERISTICS tCLK CLK t CSSC 1 2 8 3 t DIHD t DIST t SPWL t SPWH t SCLK SCLK t CSH t SDECODE CS 1 2 t SCCS 3 t DOHD 8 t DOST DIN t CSDOZ t CSDOD DOUT Hi-Z Hi-Z NOTE: SPI settings are CPOL = 0 and CPHA = 1. Figure 1. Serial Interface Timing tDISCK2ST DAISY_IN SCLK 1 tDISCK2HT LSB MSB 2 3 n n+1 n+3 n+2 tDOST DOUT MSB LSB 0 MSB (1) n = Number of channels × resolution + 24 bits.
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ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.
ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561A – JUNE 2012 – REVISED APRIL 2013 TYPICAL CHARACTERISTICS All plots are at TA = +25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.4 V, VREFN = AVSS, external clock = 2.048 MHz, data rate = 8 kSPS, and gain = 1, unless otherwise noted.
ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) All plots are at TA = +25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.4 V, VREFN = AVSS, external clock = 2.048 MHz, data rate = 8 kSPS, and gain = 1, unless otherwise noted.
ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561A – JUNE 2012 – REVISED APRIL 2013 TYPICAL CHARACTERISTICS (continued) All plots are at TA = +25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.4 V, VREFN = AVSS, external clock = 2.048 MHz, data rate = 8 kSPS, and gain = 1, unless otherwise noted. INTERNAL VREF vs TEMPERATURE 2.406 2.404 Vref (V) 2.402 2.400 2.398 2.396 2.394 2.392 ±40 ±15 10 35 60 Temperature (ƒC) 85 110 C001 Figure 15.
ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com OVERVIEW The ADS131E0x are low-power, multichannel, simultaneously-sampling, 24- and 16-bit delta-sigma (ΔΣ), analogto-digital converters (ADCs) with an integrated programmable gain amplifier (PGA). This functionality makes these devices well-suited for smart-grid and other industrial power monitor, control, and protection applications.
ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561A – JUNE 2012 – REVISED APRIL 2013 THEORY OF OPERATION This section contains details of the ADS131E0x internal functional elements. The analog blocks are discussed first, followed by the digital interface. Information on implementing power monitoring specific applications is covered towards the end of this document.
ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com Device Noise Measurements Setting CHnSET[2:0] = 001 sets the common-mode voltage of [(VREFP + VREFN) / 2] to both channel inputs. This setting can be used to test inherent device noise in the user system. Test Signals (TestP and TestN) Setting CHnSET[2:0] = 101 provides internally-generated test signals for use in sub-system verification at powerup.
ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561A – JUNE 2012 – REVISED APRIL 2013 ANALOG INPUT The ADS131E0x analog input is fully differential. Assuming PGA = 1, the differential input (INP – INN) can span between –VREF to +VREF. Refer to Table 5 for an explanation of the correlation between the analog input and digital codes. There are two general methods of driving the ADS131E0x analog input: single-ended or differential, as shown in Figure 19 and Figure 20, respectively.
ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com PGA SETTINGS AND INPUT RANGE The PGA is a differential input and output amplifier, as shown in Figure 21. It has five gain settings (1, 2, 4, 8, and 12) that can be set by writing to the CHnSET register (see the CHnSET Register in the Register Map section for details). The ADS131E0x have CMOS inputs and therefore have negligible current noise. Table 3 shows the typical bandwidth values for various gain settings.
ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561A – JUNE 2012 – REVISED APRIL 2013 Input Common-Mode Range The usable input common-mode range of the analog front-end depends on various parameters, including the maximum differential input signal, supply voltage, and PGA gain. This range is described in Equation 2: Gain VMAX_DIFF Gain VMAX_DIFF AVDD - 0.3 > CM > AVSS + 0.3 + 2 2 where: VMAX_DIFF = maximum differential signal at the PGA input CM = common-mode range (2) For example: If VDD = 3.
ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com DIGITAL DECIMATION FILTER The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for higher data rates. Higher data rates are typically used in power applications that implement software phase adjustment.
ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561A – JUNE 2012 – REVISED APRIL 2013 0 0 -20 -0.5 -40 -1 Gain (dB) Gain (dB) The sinc filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these frequencies, the filter has infinite attenuation. Figure 23 shows the sinc filter frequency response and Figure 24 shows the sinc filter roll-off. With a step change at the input, the filter takes 3 tDR to settle.
ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com 10 DR[2:0] = 000 DR[2:0] = 110 -10 Gain (dB) -30 -50 -70 -90 -110 -130 0 0.5 1 1.5 2 2.5 3 3.5 4 Normalized Frequency (fIN/fMOD) Figure 27. Transfer Function of On-Chip Decimation Filters Until 4 fMOD for DR[2:0] = 000 and DR[2:0] = 110 REFERENCE Figure 28 shows a simplified block diagram of the internal ADS131E0x reference. The reference voltage is generated with respect to AVSS.
ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561A – JUNE 2012 – REVISED APRIL 2013 100 k 22 nF +5 V 0.1 F 10 OPA350 100 +5 V VIN To VREFP Pin 10 F OUT 10 F REF5025 0.1 F 100 F 1 F TRIM Figure 29.
ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com CLOCK The ADS131E0x provide two different device clocking methods: internal and external. Internal clocking is ideally suited for low-power, battery-powered systems. The internal oscillator is trimmed for accuracy at room temperature. Accuracy varies over the specified temperature range; refer to the Electrical Characteristics for details. Clock selection is controlled by the CLKSEL pin and the CLK_EN register bit.
ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561A – JUNE 2012 – REVISED APRIL 2013 SPI INTERFACE The SPI-compatible serial interface consists of four signals: CS, SCLK, DIN, and DOUT. The interface reads conversion data, reads and writes registers, and controls the ADS131E0x operation. The DRDY output is used as a status signal to indicate when data are ready. DRDY goes low when new data are available. Chip Select (CS) Chip select (CS) selects the ADS131E0x for SPI communication.
ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com Data Output (DOUT) The data output pin (DOUT) is used with SCLK to read conversion and register data from the ADS131E0x. Data on DOUT are shifted out on the SCLK rising edge. DOUT goes to a high-impedance state when CS is high. In read data continuous mode (see the SPI Command Definitions section for more details), the DOUT output line also indicates when new data are available.
ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561A – JUNE 2012 – REVISED APRIL 2013 Figure 31 shows the relationship between DRDY, DOUT, and SCLK during data retrieval (in case of an ADS131E0x with a selected data rate that gives 16-bit resolution). DOUT is latched out at the SCLK rising edge; DRDY is pulled high at the SCLK falling edge. Note that DRDY goes high on the first SCLK falling edge regardless of whether data are being retrieved from the device or a command is being sent through the DIN pin.
ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com START The START pin must be set high (for a minimum of 2 tCLKs) or the START command sent to begin conversions. When START is low, or if the START command has not been sent, the device does not issue a DRDY signal (conversions are halted). When using the START opcode to control conversion, hold the START pin low.
ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561A – JUNE 2012 – REVISED APRIL 2013 Continuous Mode Conversions begin when the START pin is taken high or when the START opcode command is sent. As seen in Figure 34, the DRDY output goes high when conversions are started and then goes low when data are ready. Conversions continue indefinitely until the START pin is taken low or the STOP opcode command is transmitted.
ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com MULTIPLE DEVICE CONFIGURATION The ADS131E0x are designed to provide configuration flexibility when multiple devices are used in a system. The serial interface typically needs four signals: DIN, DOUT, SCLK, and CS. With one additional chip select signal per device, multiple devices can be connected together. The number of signals needed to interface n devices is 3 + n.
ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561A – JUNE 2012 – REVISED APRIL 2013 Standard Mode Figure 37a shows a configuration with two devices cascaded together. Both devices are an ADS131E0x (eightchannel) device. Together, they create a system with 16 channels. DOUT, SCLK, and DIN are shared. Each device has its own chip select. When a device is not selected by the corresponding CS being driven to logic 1, the DOUT of this device is high-impedance.
ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com Note that from Figure 2, the SCLK rising edge shifts data out of the ADS131E0x on DOUT. The SCLK rising edge is also used to latch data into the device DAISY_IN pin down the chain. This architecture allows for a faster SCLK rate speed, but it also makes the interface sensitive to board-level signal delays. The more devices in the chain, the more challenging it could become to adhere to setup and hold times.
ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561A – JUNE 2012 – REVISED APRIL 2013 SPI COMMAND DEFINITIONS The ADS131E0x provide flexible configuration control. The opcode commands, summarized in Table 9, control and configure device operation. The opcode commands are stand-alone, except for the register read and register write operations that require a second command byte plus data.
ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com START: Start Conversions This opcode starts data conversions. Tie the START pin low to control conversions by command. If conversions are in progress, this command has no effect. The STOP opcode command is used to stop conversions. If the START command is immediately followed by a STOP command, then have a gap of 4 tCLK cycles between them.
ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561A – JUNE 2012 – REVISED APRIL 2013 SDATAC: Stop Read Data Continuous This opcode cancels the Read Data Continuous mode. There are no SCLK rate restrictions for this command, but the following command must wait for 4 tCLK cycles to execute. RDATA: Read Data Issue this command after DRDY goes low to read the conversion result (in Stop Read Data Continuous mode).
ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com RREG: Read From Register This opcode reads register data. The Register Read command is a two-byte opcode followed by the register data output. The first byte contains the command opcode and the register address. The second opcode byte specifies the number of registers to read – 1. First opcode byte: 001r rrrr, where r rrrr is the starting register address.
ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561A – JUNE 2012 – REVISED APRIL 2013 REGISTER MAP Table 10 describes the various ADS131E0x registers. Table 10.
ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com CONFIG1: Configuration Register 1 Address = 01h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 1 DAISY_IN CLK_EN 1 0 DR2 DR1 DR0 This register configures each ADC channel sample rate. Bit 7 Must be set to '1' Bit 6 DAISY_IN: Daisy-chain and multiple read-back mode This bit determines which mode is enabled.
ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561A – JUNE 2012 – REVISED APRIL 2013 CONFIG2: Configuration Register 2 Address = 02h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 1 1 1 INT_TEST 0 TEST_AMP0 TEST_FREQ1 TEST_FREQ0 This register configures the test signal generation. See the Input Multiplexer section for more details. Bits[7:5] Must be set to '1' Bit 4 INT_TEST: Test source This bit determines the source for the Test signal.
ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com CONFIG3: Configuration Register 3 Address = 03h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PDB_REFBUF 1 VREF_4V 0 OPAMP_REF PDB_OPAMP 0 0 This register configures the multireference operation. Bit 7 PDB_REFBUF: Power-down reference buffer This bit determines the power-down reference buffer state.
ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561A – JUNE 2012 – REVISED APRIL 2013 FAULT: Fault Detect Control Register Address = 04h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 COMP_TH2 COMP_TH1 COMP_TH0 0 0 0 0 0 This register configures the fault detection operation. Bits[7:5] COMP_TH[2:0]: Fault detect comparator threshold These bits determine the fault detect comparator threshold level setting. See the Fault Detection section for a detailed description.
ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com CHnSET: Individual Channel Settings (n = 1 to 8) Address = 05h to 0Ch BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PDn GAINn2 GAINn1 GAINn0 0 MUXn2 MUXn1 MUXn0 This register configures the power mode, PGA gain, and multiplexer settings channels. See the Input Multiplexer section for details. CH[2:8]SET are similar to CH1SET, corresponding to the respective channels (refer to Table 10).
ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561A – JUNE 2012 – REVISED APRIL 2013 FAULT_STATP: Fault Detect Positive Input Status Address = 12h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 IN8P_FAULT IN7P_FAULT IN6P_FAULT IN5P_FAULT IN4P_FAULT IN3P_FAULT IN2P_FAULT IN1P_FAULT This register stores the status of whether the positive input on each channel has a fault or not. See the Fault Detection section for details.
ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com POWER MONITORING SPECIFIC APPLICATIONS All channels of the ADS131E0x family of devices are exactly identical, yet independently configurable, thus giving the user the flexibility of selecting any channel for voltage or current monitoring. An overview of this system is illustrated in Figure 43.
ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561A – JUNE 2012 – REVISED APRIL 2013 Neutral Phase C Phase B Phase A +1.5 V +1.8 V AVDD DVDD INP1 A N INN1 INP2 INN2 B INP3 INN3 N INP4 Device INN4 INP5 C INN5 N INP6 INN6 INN8 INN7 INP8 INP7 AVSS 1.5 V Figure 43.
ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com CURRENT SENSING Figure 44 shows a simplified diagram of typical configurations used for current sensing with a Rogowski coil, current transformer (CT), or an air coil that outputs a current or voltage. In the case of the current output transformers, the burden resistors (R1) are used for current-to-voltage conversion.
ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561A – JUNE 2012 – REVISED APRIL 2013 VOLTAGE SENSING Figure 45 shows a simplified diagram of commonly-used differential and single-ended methods of voltage sensing. A resistor divider network is used to step down the line voltage within the acceptable ADS131E0x input range and then directly connect to the inputs (INP and INN) through an antialiasing RC filter formed by resistor R3 and capacitor C.
ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com FAULT DETECTION The ADS131E0x have integrated comparators that can be used in conjunction with the external pull-up or pulldown resistors (R) to detect various fault conditions. The basic principle is to compare the input voltage with the one set by the fault comparator 3-bit digital-to-analog converter (DAC), as shown in Figure 46.
ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561A – JUNE 2012 – REVISED APRIL 2013 QUICK-START GUIDE PCB LAYOUT Power Supplies and Grounding The ADS131E0x have three supplies: AVDD, AVDD1, and DVDD. Both AVDD and AVDD1 should be as quiet as possible. AVDD1 provides the supply to the charge pump block and has transients at fCLK. Therefore, it is recommended that AVDD1 and AVSS1 be star-connected to AVDD and AVSS.
ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com Connecting the Device to Bipolar (±1.5 V or 1.8 V) Supplies Figure 48 illustrates the ADS131E0x connected to a bipolar supply. In this example, the analog supplies connect to the device analog supply (AVDD). This supply is referenced to the device analog return (AVSS), and the digital supply (DVDD) is referenced to the device digital ground return (DGND). +1.5 V +1.8 V 1 µF 0.1 µF 0.
ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561A – JUNE 2012 – REVISED APRIL 2013 POWER-UP SEQUENCING Before device power-up, all digital and analog inputs must be low. At power-up, these signals should remain low until the power supplies have stabilized, as shown in Figure 49. Once the supply voltages have reached the final value, the digital power-on reset (tPOR) executes to set the digital portion of the chip.
ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com Analog or Digital Set CLKSEL Pin = 0 and Provide External Clock f = 2.
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ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (June 2012) to Revision A Page • Deleted AGND to DGND row from Absolute Maximum Ratings table ................................................................................. 2 • Changed value of Digital input to DVDD row in Absolute Maximum Ratings table ...............................
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PACKAGE MATERIALS INFORMATION www.ti.com 21-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS131E04IPAGR TQFP PAG 64 1500 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 ADS131E06IPAGR TQFP PAG 64 1500 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 ADS131E08IPAGR TQFP PAG 64 1500 330.0 24.4 13.0 13.0 1.5 16.0 24.
PACKAGE MATERIALS INFORMATION www.ti.com 21-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS131E04IPAGR TQFP PAG 64 1500 367.0 367.0 45.0 ADS131E06IPAGR TQFP PAG 64 1500 367.0 367.0 45.0 ADS131E08IPAGR TQFP PAG 64 1500 367.0 367.0 45.
MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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