Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TQFP 48

FSO

ReferenceandBiasCircuits

Serial

Interface

LinearPhase

FIRDigitalFilter

Modulator

VREFP VREFN RBIASVMID VCAP AVDD DVDD IOVDD

DGND

AGND

AINP

AINN

FSO

SCLK

DOUT

SCLK

SYNC

CLK

DOUT

OTR

REFEN

ADS1602

www.ti.com

SBAS341E –DECEMBER 2004– REVISED OCTOBER 2011

16-Bit, 2.5MSPS Analog-to-Digital Converter

Check for Samples: ADS1602

FEATURES

DESCRIPTION

The ADS1602 is a high-speed, high-precision,

• High Speed:

delta-sigma (ΔΣ) analog-to-digital converter (ADC)

– Data Rate: 2.5MSPS

manufactured on an advanced CMOS process. The

– Bandwidth: 1.23MHz

ADS1602 oversampling topology reduces clock jitter

sensitivity during the sampling of high-frequency,

• Outstanding Performance:

large amplitude signals by a factor of four over that

– SNR: 91dB at f

= 100kHz, –1dBFS

achieved by Nyquist-rate ADCs. Consequently,

– THD: –101dB at f

= 100kHz, –6dBFS

signal-to-noise ratio (SNR) is particularly improved.

Total harmonic distortion (THD) is –101dB, and the

– SFDR: 103dB at f

= 100kHz, –6dBFS

spurious-free dynamic range (SFDR) is 103dB.

• Ease-of-Use:

Optimized for power and performance, the ADS1602

– High-Speed 3-Wire Serial Interface

dissipates only 530mW while providing a full-scale

– Directly Connects to TMS320 DSPs

differential input range of ±3V. Having such a wide

– On-Chip Digital Filter Simplifies Antialias

input range makes out-of-range signals unlikely. The

Requirements

OTR pin indicates if an analog input out-of-range

condition does occur. The differential input signal is

– Simple Pin-Driven Control—No On-Chip

measured against the differential reference, which

Registers to Program

can be generated internally or supplied externally on

– Selectable On-Chip Voltage Reference

the ADS1602.

– Simultaneous Sampling with Multiple

The ADS1602 uses an inherently stable advanced

ADS1602s

modulator with an on-chip decimation filter. The filter

• Low Power:

stop band extends to 38.6MHz, which greatly

simplifies the antialiasing circuitry. The modulator

– 530mW at 2.5MSPS

samples the input signal up to 40MSPS, depending

– Power-Down Mode

on f

CLK

, while the 16x decimation filter uses a series

of four half-band FIR filter stages to provide 75dB of

APPLICATIONS

stop band attenuation and 0.001dB of passband

ripple.

• Sonar

• Vibration Analysis

Output data is provided over a simple 3-wire serial

interface at rates up to 2.5MSPS, with a –3dB

• Data Acquisition

bandwidth of 1.23MHz. The output data or its

complementary format directly connects to DSPs

such as TI’s TMS320 family, FPGAs, or ASICs. A

dedicated synchronization pin enables simultaneous

sampling with multiple ADS1602s in multi-channel

systems. Power dissipation is set by an external

resistor that allows a reduction in dissipation when

operating at slower speeds. All of the ADS1602

features are controlled by dedicated I/O pins, which

simplify operation by eliminating the need for on-chip

registers.

The high performing, easy-to-use ADS1602 is

especially suitable for demanding measurement

applications in sonar, vibration analysis, and data

acquisition. The ADS1602 is offered in a small, 7mm

× 7mm TQFP-48 package and is specified

from –40°C to +85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (29 pages)

PAGE 1
ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com 16-Bit, 2.5MSPS Analog-to-Digital Converter Check for Samples: ADS1602 FEATURES DESCRIPTION • The ADS1602 is a high-speed, high-precision, delta-sigma (ΔΣ) analog-to-digital converter (ADC) manufactured on an advanced CMOS process. The ADS1602 oversampling topology reduces clock jitter sensitivity during the sampling of high-frequency, large amplitude signals by a factor of four over that achieved by Nyquist-rate ADCs.
PAGE 2
ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS All specifications at TA = –40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, external VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. ADS1602 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog Input Differential input voltage (VIN) (AINP – AINN) 0dBFS Common-mode input voltage (VCM) (AINP + AINN) / 2 Absolute input voltage (AINP or AINN with respect to AGND) ±VREF V 1.
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ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = –40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, external VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. ADS1602 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Digital Filter Characteristics Passband 1.1 0 f ( 40MHz ) CLK ±0.001 Passband ripple fCLK 1.15 40MHz ( –0.1dB attenuation Passband transition 1.23 –3dB attentuation 1.
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ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = –40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, external VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. ADS1602 PARAMETER TEST CONDITIONS MIN fCLK = 40MHz 45 TYP MAX UNIT 40 MHz 55 % IOVDD V Clock Input Frequency (fCLK) Duty cycle Digital Input/Output VIH 0.7 × IOVDD VIL DGND 0.3 × IOVDD IOVDD – 0.
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ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com DEFINITIONS Absolute Input Voltage Intermodulation Distortion (IMD) Absolute input voltage, given in volts, is the voltage of each analog input (AINN or AINP) with respect to AGND. IMD, given in dB, is measured while applying two input signals of the same magnitude, but with slightly different frequencies. It is calculated as the difference between the rms amplitude of the input signal to the rms amplitude of the peak spurious signal.
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ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.
PAGE 8
ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com TIMING DIAGRAMS tC CLK tHSC tSSC SYNC tSYPW tSTL FSO Figure 1. Initialization Timing TIMING REQUIREMENTS For TA = –40°C to +85°C, DVDD = 2.7V to 3.6V, and IOVDD = 2.7V to 5.25V. SYMBOL tSYPW tC DESCRIPTION MIN SYNC positive pulse width TYP MAX 1 UNIT CLK period Clock period (CLK) 25 ns tSSC Setup time; SYNC rising edge to CLK rising edge 0.5 CLK period tHSC Hold time; CLK rising edge to SYNC falling edge 0.
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ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS All specifications at TA = +25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted.
PAGE 10
ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted.
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ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted.
PAGE 12
ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted.
PAGE 13
ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted.
PAGE 14
ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted.
PAGE 15
ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com OVERVIEW The ADS1602 is a high-performance delta-sigma (ΔΣ) analog-to-digital converter (ADC). The modulator uses an inherently stable 2-1-1 multi-stage architecture incorporating proprietary circuitry that allows for very linear high-speed operation. The modulator samples the input signal at 40MSPS (when fCLK = 40MHz).
PAGE 16
ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 INPUT CIRCUITRY The ADS1602 uses switched-capacitor circuitry to measure the input voltage. Internal capacitors are charged by the inputs and then discharged internally with this cycle repeating at the frequency of CLK. Figure 39 shows a conceptual diagram of these circuits. Switches S2 represent the net effect of the modulator circuitry in discharging the sampling capacitors; the actual implementation is different.
PAGE 17
ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com REFERENCE INPUTS (VREFN, VREFP, VMID) EXTERNAL REFERENCE (REFEN = HIGH) The ADS1602 can operate from an internal or external voltage reference. In either case, the reference voltage VREF is set by the differential voltage between VREFN and VREFP: VREF = (VREFP – VREFN). VREFP and VREFN each use two pins, which should be shorted together. VMID equals approximately 2.5V and is used by the modulator.
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ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 Table 1. Maximum Allowable Clock Source Jitter for Different Input Signal Frequencies and Amplitude 392W 0.001mF ADS1602 VREFP VREFP OPA2822 10mF 4V 0.1mF 392W 0.001mF 0.1mF VMID OPA2822 10mF 2.5V www.ti.com 0.1mF INPUT SIGNAL MAXIMUM FREQUENCY MAXIMUM AMPLITUDE MAXIMUM ALLOWABLE CLOCK SOURCE JITTER 1MHz –2dB 3.8ps 1MHz –20dB 28ps 500kHz –2dB 7.
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ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com DATA RETRIEVAL STEP RESPONSE Data retrieval is controlled through a simple serial interface. The interface operates in a master fashion by outputting both a frame sync indicator (FSO) and a serial clock (SCLK). Complementary outputs are provided for the frame sync output (FSO), serial clock (SCLK), and data output (DOUT). When not needed, leave the complementary outputs unconnected.
PAGE 20
ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com 0.001 20 fCLK = 40MHz 0.0008 0 -20 0.0004 Magnitude (dB) Magnitude (dB) 0.0006 0.0002 0 -0.0002 -0.0004 -40 -60 -80 -100 -0.0006 -0.0008 -120 fCLK = 40MHz -0.001 0 200 400 600 800 1000 1200 -140 0 Frequency (kHz) fCLK = 40MHz Magnitude (dB) -0.5 -1 -1.5 -2 -2.5 -3 -3.5 900 1000 1100 60 80 100 120 Figure 51. Frequency Response Out to 120MHz 0.5 800 40 Frequency (MHz) Figure 49.
PAGE 21
ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com POWER DOWN (PD) POWER SUPPLIES When not in use, the ADS1602 can be powered down by taking the PD pin low. All circuitry is shut down, including the voltage reference. To minimize the digital current during power down, stop the clock signal supplied to the CLK input. There is an internal pull-up resistor of 170kΩ on the PD pin, but it is recommended that this pin be connected to IOVDD if not used.
PAGE 22
ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com LAYOUT ISSUES AND COMPONENT SELECTION The McBSP provides a host of functions including: • Full-duplex communication • Double-buffered data registers • Independent framing and clocking for reception and transmission of data The ADS1602 is a very high-speed, high-resolution data converter.
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ADS1602 SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (November 2010) to Revision E • Page Added footnote to Electrical Characteristics table ................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS1602IPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 ADS1602IPFBT TQFP PFB 48 250 330.0 16.4 9.6 9.6 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1602IPFBR TQFP PFB 48 1000 367.0 367.0 38.0 ADS1602IPFBT TQFP PFB 48 250 367.0 367.0 38.
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MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.