Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal HTQFP 64

FEATURES

D Data Rate: 5MSPS (10MSPS in 2X Mode)

D Signal-to-Noise Ratio: 88dB

D Total Harmonic Distortion: −99dB

D Spurious-Free Dynamic Range: 101dB

D Linear Phase with 2.45MHz Bandwidth

D Passband Ripple: ±0.0025dB

D Selectable On-Chip Reference

D Directly Connects to TMS320C6000 DSPs

D Easily Upgradable to 18 Bits with the

ADS1625 and ADS1626

D Adjustable Power Dissipation: 315 to 570mW

D Power Down Mode

D Supplies: Analog +5V

Digital +3V

Digital I/O +2.7V to +5.25V

APPLICATIONS

D Scientific Instruments

D Automated Test Equipment

D Data Acquisition

D Medical Imaging

D Vibration Analysis

DESCRIPTION

The ADS1605 and ADS1606 are high-speed, high-pre-

cision, delta-sigma analog-to-digital converters (ADCs)

with 16-bit resolution. The data rate is 5 mega-samples

per second (MSPS), the bandwidth (−3dB) is 2.45MHz,

and passband ripple is less than ±0.0025dB (to

2.2MHz). Both devices offer the same outstanding per-

formance at these speeds with a signal-to-noise ratio up

to 88dB, total harmonic distortion down to −99dB, and

a spurious-free dynamic range up to 101dB. For even

higher-speed operation, the data rate can be doubled to

10MSPS in 2X mode. The ADS1606 includes an adjust-

able first-in first-out buffer (FIFO) for the output data.

The input signal is measured against a voltage refer-

ence that can be generated on-chip or supplied exter-

nally. The digital output data are provided over a simple

parallel interface that easily connects to digital signal

processors (DSPs). An out-of-range monitor reports

when the input range has been exceeded. The

ADS1605/6 operate from a +5V analog supply (AVDD)

and +3V digital supply (DVDD). The digital I/O supply

(IOVDD) operates from +2.7 to +5.25V, enabling the

digital interface to support a range of logic families. The

analog power dissipation is set by an external resistor

and can be reduced when operating at slower speeds.

A power down mode, activated by a digital I/O pin, shuts

down all circuitry. The ADS1605/6 are offered in a

TQFP-64 package using TI PowerPAD technology.

The ADS1605 and ADS1606, along with their 18-bit

counterparts, the ADS1625 and ADS1626, are well

suited for the demanding measurement requirements

of scientific instrumentation, automated test equip-

ment, data acquisition, and medical imaging.

REFEN

FIFO_LEV[2:0]

DOUT[15:0]

OTR

DRDY

2XMODE

CLK

RESET

ADS1606 Only

FIFO

I/O

Interface

Digital

Filter

Modulator

Reference and Bias Circuits

DGNDAGND

AVDD DVDD IOVDDVCAPRBIASVMIDVREFNVREFP

AINP

AINN

ADS1605

ADS1606

ADS1605

ADS1606

SBAS274H − MARCH 2003 − REVISED MAY 2007

16-Bit, 5MSPS

Analog-to-Digital Converter

         

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www.ti.com

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

Summary of content (38 pages)

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ADS1605 ADS1606 SBAS274H − MARCH 2003 − REVISED MAY 2007 16-Bit, 5MSPS Analog-to-Digital Converter FEATURES DESCRIPTION D D D D D D D D D The ADS1605 and ADS1606 are high-speed, high-precision, delta-sigma analog-to-digital converters (ADCs) with 16-bit resolution. The data rate is 5 mega-samples per second (MSPS), the bandwidth (−3dB) is 2.45MHz, and passband ripple is less than ±0.0025dB (to 2.2MHz).
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 ELECTRICAL CHARACTERISTICS All specifications at −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, 2XMODE = low, VCM = 2.0V, FIFO disabled, and RBIAS = 37kΩ, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog Input 0dBFS Differential input voltage (VIN) (AINP − AINN) −2dBFS −6dBFS −20dBFS ±1.467VREF ±1.165VREF V ±0.735VREF ±0.147VREF V 2.
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 ELECTRICAL CHARACTERISTICS (continued) All specifications at −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, 2XMODE = low, VCM = 2.0V, FIFO disabled, and RBIAS = 37kΩ, unless otherwise noted.
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 ELECTRICAL CHARACTERISTICS (continued) All specifications at −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, 2XMODE = low, VCM = 2.0V, FIFO disabled, and RBIAS = 37kΩ, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Voltage Reference(1) VREF = (VREFP − VREFN) VREFP 2.5 3.0 3.2 V 3.75 4.0 4.25 V VREFN 0.75 1.0 1.25 V VMID 2.3 2.5 2.
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 DEFINITIONS Absolute Input Voltage Absolute input voltage, given in volts, is the voltage of each analog input (AINN or AINP) with respect to AGND. Aperture Delay Aperture delay is the delay between the rising edge of CLK and the sampling of the input signal.
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 PARAMETER MEASUREMENT INFORMATION t2 t1 CLK t2 t3 t4 DRDY t4 t6 t5 DOUT[15:0] Data N + 1 Data N Data N + 2 NOTE: CS and RD tied low. Figure 1. Data Retrieval Timing (ADS1605, ADS1606 with FIFO Disabled) RD, CS t7 t8 DOUT[15:0] Figure 2.
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 CLK t11 RESET t9 t12 t 10 DRDY t3 Settled Data DOUT[15:0] NOTE: CS and RD tied low. Figure 3. Reset TIming (ADS1605, ADS1606 with FIFO Disabled) TIMING REQUIREMENTS FOR FIGURE 3 SYMBOL DESCRIPTION t3 Rising edge of CLK to DRDY low t9 RESET pulse width t10 Delay from RESET active (low) to DRDY forced high and DOUT forced low t11 RESET rising edge to falling edge of CLK t12 Delay from DOUT active to valid DOUT (settling to 0.
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 t1 t2 CLK t2 t 13 t14 DRDY t15 t16 CS(1) t21 t 17 RD t20 t18 DOUT[15:0] t19 D1 DL(2) D2 (1) CS may be tied low. (2) The number of data readings (DL) is set by the FIFO level. Figure 4. Data Retrieval Timing (ADS1606 with FIFO Enabled) RD, CS t7 t8 DOUT[15:0] Figure 5.
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 CLK t11 RESET t9 t26 t25 DRDY t23 RD t24 Figure 6.
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 TYPICAL CHARACTERISTICS All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, 2XMODE = low, VCM = 2.0V, and RBIAS = 37kΩ, unless otherwise noted.
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 TYPICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, 2XMODE = low, VCM = 2.0V, and RBIAS = 37kΩ, unless otherwise noted. INTERMODULATION RESPONSE NOISE HISTOGRAM 0 18k VIN = 0V Power Spectral Density (dB) 16k Occurrences 14k 12k 10k 8k 6k 4k 2k −4 −3 −2 −1 0 1 2 3 4 −40 −60 −80 −100 −120 −140 −160 1.95 1.96 1.97 1.98 1.99 2.00 2.01 2.02 2.03 2.
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 TYPICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, 2XMODE = low, VCM = 2.0V, and RBIAS = 37kΩ, unless otherwise noted.
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 TYPICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, 2XMODE = low, VCM = 2.0V, and RBIAS = 37kΩ, unless otherwise noted.
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 TYPICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, 2XMODE = low, VCM = 2.0V, and RBIAS = 37kΩ, unless otherwise noted. INTEGRAL NONLINEARITY 1.0 f IN = 100Hz, −1.5dBFS 0.4 0.6 0.3 0.4 0.2 DNL (LSB) INL (LSB) 0.8 DIFFERENTIAL NONLINEARITY 0.5 0.2 0 −0.2 0.1 0 −0.1 −0.4 −0.2 −0.6 −0.3 −0.8 −0.4 −0.5 −1.
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 OVERVIEW The ADS1605 and ADS1606 are high-performance deltasigma ADCs with a default oversampling ratio of 8. The modulator uses an inherently stable 2-1-1 pipelined deltasigma modulator architecture incorporating proprietary circuitry that allows for very linear high-speed operation. The modulator samples the input signal at 40MSPS (when fCLK = 40MHz).
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 INPUT CIRCUITRY The ADS1605/6 uses switched-capacitor circuitry to measure the input voltage. Internal capacitors are charged by the inputs and then discharged internally with this cycle repeating at the frequency of CLK. Figure 8 shows a conceptual diagram of these circuits. Switches S2 represent the net effect of the modulator circuitry in discharging the sampling capacitors; the actual implementation is different.
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 REFERENCE INPUTS (VREFN, VREFP, VMID) The ADS1605/6 can operate from an internal or external voltage reference. In either case, the reference voltage VREF is set by the differential voltage between VREFN and VREFP: VREF = (VREFP – VREFN). VREFP and VREFN each use two pins, which should be shorted together. VMID equals approximately 2.5V and is used by the modulator.
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 CLOCK INPUT (CLK) The ADS1605/6 requires an external clock signal to be applied to the CLK input pin. The sampling of the modulator is controlled by this clock signal. As with any highspeed data converter, a high quality clock is essential for optimum performance. Crystal clock oscillators are the recommended CLK source; other sources such as frequency synthesizers are usually not adequate.
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 RESETTING THE ADS1605 RESETTING THE ADS1606 The ADS1605 and ADS1606 (with FIFO disabled) are asynchronously reset when the RESET pin is taken low. During reset, all of the digital circuits are cleared, DOUT[15:0] are forced low, and DRDY forced high. It is recommended that the RESET pin be released on the falling edge of CLK. Afterwards, DRDY goes low on the second rising edge of CLK.
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 SETTLING TIME IMPULSE RESPONSE The settling time is an important consideration when measuring signals with large steps or when using a multiplexer in front of the analog inputs. The ADS1605/6 digital filter requires time for an instantaneous change in signal level to propagate to the output. Figure 18 plots the normalized response for an input applied at t = 0 with 2XMODE = low.
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 FREQUENCY RESPONSE 0.0025 0.0015 0.0010 0.0005 0 −0.0005 −0.0010 −0.0015 −0.0020 Figure 20 shows the passband ripple from dc to 2.2MHz (fCLK = 40MHz). Figure 21 shows a closer view of the passband transition by plotting the response from 2.0MHz to 2.5MHz (fCLK = 40MHz). 0 0.5 1.0 1.5 2.0 2.5 Frequency (MHz) Figure 20. Passband Ripple 1 0 −1 Magnitude (dB) The overall frequency response repeats at multiples of the CLK frequency.
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 FIFO (ADS1606 ONLY) The ADS1606 includes an adjustable level first-in firstout buffer (FIFO) for the output data. The FIFO allows data to be temporarily stored within the ADS1606 to provide more flexibility for the host controller when retrieving data. Pins FIFO_LEV[2:0] set the level or depth of the FIFO. Note that these pins must be left unconnected on the ADS1605. The FIFO is enabled by setting at least one of the FIFO_LEV inputs high.
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 32/fCLK 128/fCLK DRDY RD Figure 24. Example of Skipping Readback when FIFO Level = 4 32/fCLK 64/fCLK DRDY RD FIFO_LEV[2:0] 010 (Level = 4) 100 (Level = 8) Change FIFO_LEV[2:0] here Figure 25. Example of Synchronized Change of FIFO Level from 4 to 8 ANALOG POWER DISSIPATION An external resistor connected between the RBIAS pin and the analog ground sets the analog current level, as shown in Figure 26.
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 POWER SUPPLIES main supply bus should also be bypassed with a bank of capacitors from 47µF to 0.1µF, as shown. Three supplies are used on the ADS1605/6: analog (AVDD), digital (DVDD) and digital I/O (IOVDD). Each supply must be suitably bypassed to achieve the best performance. It is recommended that a 1µF and 0.1µF ceramic capacitor be placed as close to each supply pin as possible.
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 2X MODE The 2XMODE digital input determines the performance (16-bit or 14-bit) by setting the oversampling ratio. When 2XMODE = low, the oversampling ratio = 8 for 16-bit performance. When 2XMODE = high, the oversampling ratio = 4 for 14-bit performance. Note that when 2XMODE is high, all 16 bits of DOUT remain active. Decreasing the oversampling ratio from 8 to 4 doubles the data rate in 2X mode.
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 APPLICATIONS INFORMATION INTERFACING THE ADS1605 TO THE TMS320C6000 Figure 28 illustrates how to directly connect the ADS1605 to the TMS320C6000 DSP. The processor controls reading using output ARE. The ADS1605 is selected using the DSP control output, CE2. The ADS1605 16-bit data output bus is directly connected to the TMS320C6000 data bus. The data ready output from the ADS1605, DRDY, drives interrupt EXT_INT7 on the TMS320C6000.
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 INTERFACING THE ADS1605 TO THE TMS320C5400 INTERFACING THE ADS1606 TO THE TMS320C5400 Figure 30 illustrates how to connect the ADS1605 to the TMS320C5400 DSP. The processor controls the reading using the outputs R/W and IS. The I/O space select signal (IS) is optional and is used to prevent the ADS1605 RD input from being strobed when the DSP is accessing other external memory spaces (address or data).
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"#$%& "#$%$ www.ti.com SBAS274H − MARCH 2003 − REVISED MAY 2007 Revision History DATE REV PAGE SECTION 5/15/07 H 24 Readback Considerations DESCRIPTION Added last three sentences. NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS1605IPAPR HTQFP PAP 64 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 ADS1605IPAPT HTQFP PAP 64 250 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 ADS1606IPAPT HTQFP PAP 64 250 330.0 24.4 13.0 13.0 1.5 16.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1605IPAPR HTQFP PAP 64 1000 367.0 367.0 45.0 ADS1605IPAPT HTQFP PAP 64 250 367.0 367.0 45.0 ADS1606IPAPT HTQFP PAP 64 250 367.0 367.0 45.
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