Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TQFP 64

ADS1672

Modulator

DVDD

DGND

AINP

AINN

ADS1672

AGND

AVDD

VREFP

VREFN

Dual

Path

Filter

Low-LatencyFilter

Wide-BandwidthFilter

CMOSand

LVDS

Compatible

Serial

Interface

DataReady

DataOutput

SerialShiftClock

ChipSelect

InterfaceConfiguration

MasterClock

FilterPath

DataRate

StartConversion

PowerDown

Out-of-Range

Control

ADS1672

www.ti.com

SBAS402D –JUNE 2008–REVISED JULY 2010

625kSPS, 24-Bit Analog-to-Digital Converter

Check for Samples: ADS1672

FEATURES

DESCRIPTION

• AC Performance:

The ADS1672 is a high-speed, high-precision

107dB of Dynamic Range at 625kSPS

analog-to-digital converter (ADC). Using an advanced

115.5dB of Dynamic Range at 78kSPS

delta-sigma (ΔΣ) architecture, it operates at speeds

up to 625kSPS with outstanding ac performance and

–113dB THD

dc accuracy.

• DC Accuracy:

3ppm INL

The ADS1672 ADC is comprised of a low-drift,

2mV/°C Offset Drift

chopper-stabilized modulator with out-of-range

detection and a dual-path programmable digital filter.

2ppm/°C Gain Drift

The dual filter path allows the user to select between

• Programmable Digital Filter with

two post-processing filters: low-latency or

User-Selectable Path:

wide-bandwidth. The low-latency filter settles quickly

– Low-Latency: Completely settles in 5.5ms

in one cycle, for applications with large instantaneous

changes, such as a multiplexer. The wide-bandwidth

– Wide-Bandwidth: 305kHz BW with flat

path provides an optimized frequency response for ac

passband

measurements with a passband ripple of less than

• Flexible Read-Only Serial Interface:

0.001dB, stop band attenuation of 86dB, and a

– Standard CMOS

bandwidth of 305kHz.

– Serialized LVDS

The ADS1672 is controlled through I/O pins—there

• Easy Conversion Control with START Pin

are no registers to program. A dedicated START pin

allows for direct control of conversions: toggle the

• Out-of-Range Detection

START pin to begin a conversion, and then retrieve

• Supply: Analog +5V, Digital +3V

the output data. The flexible serial interface supports

• Power: 350mW

data readback with either standard CMOS and LVDS

logic levels, allowing the ADS1672 to directly connect

APPLICATIONS

to a wide range of microcontrollers, digital signal

processors (DSPs), or field-programmable grid arrays

• Automated Test Equipment

(FPGAs).

• Vibration Analysis

The ADS1672 operates from an analog supply of 5V

• Sonar

and digital supply of 3V, and dissipates 350mW of

• Test and Measurement

power. When not in use, the PDWN pin can be used

to power down all device circuitry. The device is fully

specified over the industrial temperature range and is

offered in a TQFP-64 package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (33 pages)

PAGE 1
ADS1672 AD S1 672 www.ti.com SBAS402D – JUNE 2008 – REVISED JULY 2010 625kSPS, 24-Bit Analog-to-Digital Converter Check for Samples: ADS1672 FEATURES DESCRIPTION • The ADS1672 is a high-speed, high-precision analog-to-digital converter (ADC). Using an advanced delta-sigma (ΔΣ) architecture, it operates at speeds up to 625kSPS with outstanding ac performance and dc accuracy. 1 2 • • • • • • • AC Performance: 107dB of Dynamic Range at 625kSPS 115.
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ADS1672 SBAS402D – JUNE 2008 – REVISED JULY 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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ADS1672 www.ti.com SBAS402D – JUNE 2008 – REVISED JULY 2010 ELECTRICAL CHARACTERISTICS All specifications are at TA = –40°C to +85°C, AVDD = 5V, DVDD = 3V, fCLK = 20MHz, VREF = +3V, and RBIAS = 7.5kΩ, unless otherwise noted. ADS1672 PARAMETER TEST CONDITIONS MIN TYP ANALOG INPUTS Full-scale input voltage Common-mode input voltage MAX UNIT . VIN = (AINP – AINN) ±VREF V VCM = (AINP + AINN)/2 2.
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ADS1672 SBAS402D – JUNE 2008 – REVISED JULY 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications are at TA = –40°C to +85°C, AVDD = 5V, DVDD = 3V, fCLK = 20MHz, VREF = +3V, and RBIAS = 7.5kΩ, unless otherwise noted. ADS1672 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CLOCK (CLK) VIH 0.7AVDD AVDD V VIL AGND 0.3AVDD V V DIGITAL INPUTS VIH 0.7DVDD DVDD VIL DGND 0.3DVDD V ±10 mA Input leakage DGND < VIN < DVDD CMOS OUTPUTS VOH IOH = 2mA VOL IOL = 2mA 0.
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ADS1672 www.ti.
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ADS1672 SBAS402D – JUNE 2008 – REVISED JULY 2010 www.ti.com Table 1. TERMINAL FUNCTIONS (continued) PIN NAME NO. FUNCTION LL_CONFIG 32 Digital Input Configure low-latency digital filter. If LL_CONFIG = '0', then single-cycle settling is selected. If LL_CONFIG = '1', then fast-response is selected. FPATH 33 Digital Input Digital filter path selection. If FPATH = '0', then path is wide-bandwidth. If FPATH = '1', then path is low-latency.
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ADS1672 www.ti.com SBAS402D – JUNE 2008 – REVISED JULY 2010 TIMING CHARACTERISTICS tCLK CLK tCLKDR tDRPW DRDY tSCLK tDRSCLK SCLKinternal tDOPD tDOHD MSB DOUT LSB Figure 1. Data Retrieval Timing with Internal SCLK (SCLK_SEL = 0) TIMING REQUIREMENTS: Internal SCLK At TA = –40°C to +85°C, and DVDD = 2.7V to 3.3V.
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ADS1672 SBAS402D – JUNE 2008 – REVISED JULY 2010 www.ti.com tCLK CLK tCLKDR tSCLKDR DRDY tDRPW CS (1) tCSSC tSPW tSPW SCLKexternal tSCLK tDOPD DOUT Hi-Z tCSRDO MSB LSB tCSFDO (1) CS may be tied low. Figure 2. Data Retrieval Timing with External SCLK (SCLK_SEL = 1) TIMING REQUIREMENTS: External SCLK At TA = –40°C to +85°C, and DVDD = 2.7V to 3.3V.
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ADS1672 www.ti.com SBAS402D – JUNE 2008 – REVISED JULY 2010 TYPICAL CHARACTERISTICS All specifications are at TA = –40°C to +85°C, AVDD = 5V, DVDD = 3V, fCLK = 20MHz, VREF = +3V, and RBIAS = 7.5kΩ, unless otherwise noted. OUTPUT SPECTRUM (1k, –0.5dBFS SIGNAL) OUTPUT SPECTRUM DETAIL VIEW (1k, –0.5dBFS SIGNAL) 0 0 fIN = 1kHz, -0.5dBFS THD = -109.1dBc 65,536 points -40 -60 -80 -100 fIN = 1kHz, -0.5dBFS THD = -109.
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ADS1672 SBAS402D – JUNE 2008 – REVISED JULY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) All specifications are at TA = –40°C to +85°C, AVDD = 5V, DVDD = 3V, fCLK = 20MHz, VREF = +3V, and RBIAS = 7.5kΩ, unless otherwise noted. SNR and |THD| vs INPUT AMPLITUDE SNR and |THD| vs INPUT COMMON-MODE 140 115 fIN = 10kHz fIN = 10kHz |THD|, AIN = -6dBFS SNR, |THD| (dBc) SNR, |THD| (dBc) 120 100 |THD| 80 SNR 60 110 |THD|, AIN = -0.5dBFS 105 SNR, AIN = -0.
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ADS1672 www.ti.com SBAS402D – JUNE 2008 – REVISED JULY 2010 TYPICAL CHARACTERISTICS (continued) All specifications are at TA = –40°C to +85°C, AVDD = 5V, DVDD = 3V, fCLK = 20MHz, VREF = +3V, and RBIAS = 7.5kΩ, unless otherwise noted. NOISE HISTOGRAM (OSR = 256) Wide Bandwidth fDATA = 78.125kSPS s = 10.8 Output Codes 65k Points Number of Occurrences 4500 4000 3500 3000 2500 2000 1500 1000 116 Dynamic Range (dBFS) 5000 DYNAMIC RANGE vs OVERSAMPLING RATIO 78.125kHz: OSR = 256 156.25kHz: OSR = 128 312.
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ADS1672 SBAS402D – JUNE 2008 – REVISED JULY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) All specifications are at TA = –40°C to +85°C, AVDD = 5V, DVDD = 3V, fCLK = 20MHz, VREF = +3V, and RBIAS = 7.5kΩ, unless otherwise noted. |THD| vs RBIAS SNR vs RBIAS 104 115 fCLK = 10MHz 100 110 SNR (dBc) |THD| (dBc) fCLK = 2.5MHz 102 fCLK = 2.5MHz fCLK = 10MHz 98 96 105 94 fCLK = 20MHz fCLK = 20MHz 92 fIN = 10kHz, AIN = -0.
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ADS1672 www.ti.com SBAS402D – JUNE 2008 – REVISED JULY 2010 OVERVIEW The ADS1672 is a 24-bit, ΔΣ analog-to-digital converter (ADC). It provides high-resolution measurements of both ac and dc signals and features an advanced multi-stage analog modulator with a programmable and flexible digital decimation filter. A dedicated START pin allows precise conversion control; toggle the pin to begin the conversion process.
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ADS1672 SBAS402D – JUNE 2008 – REVISED JULY 2010 www.ti.com NOISE PERFORMANCE ANALOG INPUTS (AINP, AINN) The ADS1672 offers outstanding noise performance that can be optimized by adjusting the data rate. As the averaging is increased (thus reducing the data rate), the noise drops correspondingly. Table 2 shows the noise as a function of data rate for both the low-latency and the wide-bandwidth filter paths under the conditions shown.
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ADS1672 www.ti.com SBAS402D – JUNE 2008 – REVISED JULY 2010 VOLTAGE REFERENCE INPUTS (VREFN, VREFP) CONVERSION START The voltage reference for the ADS1672 is the differential voltage between VREFP and VREFN: VREF = (VREFP – VREFN) (2) A high-quality reference voltage with the appropriate drive strength is essential for achieving the best performance from the ADS1672. Noise and drift on the reference degrade overall system performance.
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ADS1672 SBAS402D – JUNE 2008 – REVISED JULY 2010 www.ti.com DIGITAL FILTER LOW-LATENCY DIGITAL FILTER In delta-sigma ADCs, the digital filter has a critical influence on device performance. The digital filter sets the frequency response, data rate, bandwidth, and settling time. Choosing to optimize some of these features in a filter means that compromises must be made with other specifications. These tradeoffs determine the applications for which the device is best suited.
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ADS1672 www.ti.com SBAS402D – JUNE 2008 – REVISED JULY 2010 The second configuration is fast response. The DRATE[1:0] digital input pins select the data rate for the Fast Response Configuration, as shown in Table 6. When selected, this configuration provides a higher output data rate. The faster output data rate allows for more averaging by a post-processor within a given time interval to reduce noise.
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ADS1672 SBAS402D – JUNE 2008 – REVISED JULY 2010 www.ti.com It is important to note, however, that the absolute settling time of the low-latency path does not change when using the fast response configuration. Changes on the input signal during conversions after the initial settling require multiple cycles to fully settle. To help illustrate this requirement, consider a change on the inputs as shown in Figure 29, where START is assumed to have been taken high before the input voltage was changed.
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ADS1672 www.ti.com SBAS402D – JUNE 2008 – REVISED JULY 2010 Phase Response 20 0 -20 Magnitude (dB) The low-latency filter uses a multiple stage linear phase digital filter. Linear phase filters exhibit constant delay time versus input frequency (also know as constant group delay). This feature of linear phase filters means that the time delay from any instant of the input signal to the corresponding same instant of the output data is constant and independent of the input signal frequency.
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ADS1672 SBAS402D – JUNE 2008 – REVISED JULY 2010 www.ti.com Settling Time The overall frequency response repeats at the modulator sampling rate, which is the same as the input clock frequency. Figure 33 shows the response with the fastest data rate selected (625kSPS when fCLK = 20MHz). The Wide-Bandwidth filter fully settles before indicating data are ready for retrieval after the START pin is taken high, as shown in Figure 35.
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ADS1672 www.ti.com SBAS402D – JUNE 2008 – REVISED JULY 2010 OTRD FUNCTION The ADS1672 provides an out-of-range (OTRD) pin that can be used in feedback loops to set the dynamic range of the input signal. The OTRD function is triggered when the output code of the digital filter exceeds the positive or negative full-scale range. OTRD goes high on the rising edge of DRDY. When the digital output code returns within the full-scale range, OTRD returns low on the next rising edge of DRDY.
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ADS1672 SBAS402D – JUNE 2008 – REVISED JULY 2010 www.ti.com SERIAL SHIFT CLOCK (SCLK, SCLK, SCLK_SEL) The serial shift clock SCLK is used to shift out the conversion data, MSB first, onto the Data Output pins. Either an internally- or externally-generated shift clock can be selected using the SCLK_SEL pin. If SCLK_SEL is set to '0', a free-running shift clock is generated internally from the master clock and outputs on the SCLK and SCLK pins.
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ADS1672 www.ti.com SBAS402D – JUNE 2008 – REVISED JULY 2010 SYNCHRONIZING MULTIPLE ADS1672s ANALOG POWER DISSIPATION The START pin should be applied at power-up and resets the ADS1672 filters. START begins the conversion process, and the START pin enables simultaneous sampling with multiple ADS1672s in multichannel systems. All devices to be synchronized must use a common CLK input.
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ADS1672 SBAS402D – JUNE 2008 – REVISED JULY 2010 www.ti.com POWER SUPPLIES blank Two supplies are used on the ADS1672: analog (AVDD) and digital (DVDD). Each supply must be suitably bypassed to achieve the best performance. It is recommended that a 1mF and 0.1mF ceramic capacitor be placed as close to each supply pin as possible. Connect each supply-pin bypass capacitor to the associated ground. Each main supply bus should also be bypassed with a bank of capacitors from 47mF to 0.1mF.
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ADS1672 www.ti.com SBAS402D – JUNE 2008 – REVISED JULY 2010 APPLICATIONS INFORMATION To obtain the specified performance from the ADS1672, the following layout and component guidelines should be considered. 1. Power Supplies: The device requires two power supplies for operation: DVDD and AVDD. For both supplies, use a 10mF tantalum capacitor, bypassed with a 0.1mF ceramic capacitor, placed close to the device pins. Alternatively, a single 10mF ceramic capacitor can be used.
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ADS1672 SBAS402D – JUNE 2008 – REVISED JULY 2010 www.ti.com 1kW 10nF +5V 0.1mF 100W OPA211 100W OUT 100mF 10mF 22mF VIN +5V TRIM 22mF REF5030 0.1mF 1mF 1mF 20MHz Clock Source 64 63 62 61 60 59 55 VREFP VREFP CAP2 VREFN VREFN CAP1 CLK 10W 4 AINN VINN Differential Inputs 10W VINP 100pF 750pF 5 AINP 100pF ADS1672 8 RBIAS 7.5kW 13 VCM 1mF Figure 39. Basic Analog Signal Connection RG 383W RS 50W RF 392W RT 54.
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ADS1672 www.ti.com SBAS402D – JUNE 2008 – REVISED JULY 2010 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (June, 2009) to Revision D Page • Changed THD performance from –115dB to –113dB in Features list .................................................................................. 1 • Revised Description text to reflect 86dB stop band attenuation ..............................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS1672IPAGR Package Package Pins Type Drawing TQFP PAG 64 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1500 330.0 24.4 Pack Materials-Page 1 13.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.0 1.5 16.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1672IPAGR TQFP PAG 64 1500 367.0 367.0 45.
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MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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