Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External TQFP 64

Modulator

AINP

AINN

ADS1675

DVDD

DGND

AGND

AVDDVREFP VREFN

Dual

Path

Filter

Low-Latency

Filter

Wide-Bandwidth

Filter

CMOSand

LVDS

Compatible

Serial

Interface

DataReady

DataOutput

SerialShiftClock

ChipSelect

InterfaceConfiguration

MasterClock

FilterPath

DataRate

StartConversion

PowerDown

Out-of-Range

Control

CLK

PLL

ADS1675

www.ti.com

SBAS416D –DECEMBER 2008–REVISED AUGUST 2010

4MSPS, 24-Bit Analog-to-Digital Converter

Check for Samples: ADS1675

FEATURES

DESCRIPTION

• AC Performance:

The ADS1675 is a high-speed, high-precision

103dB of Dynamic Range at 4MSPS

analog-to-digital converter (ADC). Using an advanced

111dB of Dynamic Range at 125kSPS

delta-sigma (ΔΣ) architecture, it operates at speeds

up to 4MSPS with outstanding ac performance and

–107dB THD

dc accuracy.

• DC Accuracy:

3ppm INL

The ADS1675 ADC is comprised of a low-drift

4mV/°C Offset Drift

modulator with out-of-range detection and a dual-path

programmable digital filter. The dual filter path allows

4ppm/°C Gain Drift

the user to select between two post-processing filters:

• Programmable Digital Filter with

Low-Latency or Wide-Bandwidth. The Low-Latency

User-Selectable Path:

filter settles quickly (as fast as 2.65ms) for

– Low-Latency: Completely settles in 2.65ms

applications with large instantaneous changes, such

as a multiplexer. The Wide-Bandwidth path provides

– Wide-Bandwidth: 1.7MHz BW with flat

an optimized frequency response for ac

passband

measurements with a passband ripple of less than

• Flexible Read-Only Serial Interface:

±0.00002dB, stop band attenuation of 86dB, and a

– Standard CMOS

bandwidth of 1.7MHz.

– Serialized LVDS

The device offers two speed modes with distinct

• Easy Conversion Control with START Pin

interface, resolution, and feature set. In the

high-speed mode the device can be set to operate at

• Out-of-Range Detection

either 4MSPS or 2MSPS. In the low-speed mode, it

• Supply: Analog +5V, Digital +3V

can be set to operate at either 1MSPS, 500KSPS,

• Power: 575mW

250KSPS or 125KSPS.

The ADS1675 is controlled through I/O pins—there

APPLICATIONS

are no registers to program. A dedicated START pin

• Automated Test Equipment

allows for direct control of conversions: toggle the

• Medical Imaging

START pin to begin a conversion, and then retrieve

the output data. The flexible serial interface supports

• Scientific Instrumentation

data readback with either standard CMOS and LVDS

• Test and Measurement

logic levels, allowing the ADS1675 to directly connect

to a wide range of microcontrollers, digital signal

processors (DSPs), or field-programmable grid arrays

(FPGAs).

The ADS1675 operates from an analog supply of 5V

and digital supply of 3V, and dissipates 575mW of

power. When not in use, the PDWN pin can be used

to power down all device circuitry. The device is fully

specified over the industrial temperature range and is

offered in a TQFP-64 package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (37 pages)

PAGE 1
ADS1675 www.ti.com SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 4MSPS, 24-Bit Analog-to-Digital Converter Check for Samples: ADS1675 FEATURES DESCRIPTION • The ADS1675 is a high-speed, high-precision analog-to-digital converter (ADC). Using an advanced delta-sigma (ΔΣ) architecture, it operates at speeds up to 4MSPS with outstanding ac performance and dc accuracy.
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ADS1675 SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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ADS1675 www.ti.com SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 ELECTRICAL CHARACTERISTICS All specifications are at TA = –40°C to +85°C, AVDD = 5V, DVDD = 3V, fCLK = 32MHz, VREF = +3V, and RBIAS = 7.5kΩ, unless otherwise noted. ADS1675 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Full-scale input voltage Common-mode input voltage VIN = (AINP – AINN) ±VREF V VCM = (AINP + AINN)/2 2.
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ADS1675 SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications are at TA = –40°C to +85°C, AVDD = 5V, DVDD = 3V, fCLK = 32MHz, VREF = +3V, and RBIAS = 7.5kΩ, unless otherwise noted.
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ADS1675 www.ti.
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ADS1675 SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 www.ti.com TERMINAL FUNCTIONS (continued) PIN NAME NO. FUNCTION LL_CONFIG 32 Digital input Configure Low-Latency digital filter. (1) If LL_CONFIG = '0', then single-cycle settling is selected. If LL_CONFIG = '1', then fast-response is selected. FPATH 33 Digital input Digital filter path selection. If FPATH = '0', then path is Wide-Bandwidth. If FPATH = '1', then path is Low-Latency.
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ADS1675 www.ti.com SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 TIMING CHARACTERISTICS tLSCLKDC tLSCLK SCLK tLDRPW DRDY tLSCLKDR tLDOPD DOUT MSB LSB MSB (1) High-speed LVDS valid only for DRATE = 100 and DRATE = 101. (2) Timing shown is the single-end version of the LVDS signal pairs. Figure 1. High-Speed LVDS Data Retrieval Timing TIMING REQUIREMENTS: High-Speed LVDS At TA = –40°C to +85°C, and DVDD = 2.85V to 3.15V.
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ADS1675 SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 www.ti.com tCLK tDC CLK tLCLKDR tLDRPW DRDY CS tLSCLK tDRSCLK tSPWH SCLKinternal tLDOPD DOUT MSB LSB Figure 3. Low-Speed Mode Data Retrieval Timing with Internal SCLK (SCLK_SEL = 0) TIMING REQUIREMENTS: Internal SCLK At TA = –40°C to +85°C, and DVDD = 2.85V to 3.15V. SYMBOL DESCRIPTION MIN tDC CLK duty cycle tSPWH SCLK pulse width high tCLK CLK period (1/fCLK) 31.
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ADS1675 www.ti.com SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 tCLK CLK tCLKDR tLSCLKDR DRDY tLDRPW CS (1) tCSSC tSPW tSPW SCLKEXTERNAL tLSCLK tLDOPD DOUT Hi-Z tCSRDO MSB LSB tCSFDO (3) CS may be tied low. Figure 4. Low-Speed Mode Data Retrieval Timing with External SCLK (SCLK_SEL = 1) TIMING REQUIREMENTS: External SCLK At TA = –40°C to +85°C, and DVDD = 2.85V to 3.15V. SYMBOL DESCRIPTION MIN TYP MAX UNIT tCLK CLK period (1/fCLK) 31.
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ADS1675 SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS All specifications are at TA = –40°C to +85°C, AVDD = 5V, DVDD = 3V, fCLK = 32MHz, VREF = +3V, and RBIAS = 7.5kΩ, unless otherwise noted. SPECTRAL RESPONSE (DRATE = 000, WB Filter) 0 0 fIN = 1kHz, -0.5dBFS THD = -106.8dBc 65,536 Points -20 fIN = 1kHz, -6dBFS THD = -106.
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ADS1675 www.ti.com SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 TYPICAL CHARACTERISTICS (continued) All specifications are at TA = –40°C to +85°C, AVDD = 5V, DVDD = 3V, fCLK = 32MHz, VREF = +3V, and RBIAS = 7.5kΩ, unless otherwise noted.
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ADS1675 SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) All specifications are at TA = –40°C to +85°C, AVDD = 5V, DVDD = 3V, fCLK = 32MHz, VREF = +3V, and RBIAS = 7.5kΩ, unless otherwise noted. SPECTRAL RESPONSE (DRATE = 101, WB Filter) SPECTRAL RESPONSE (DRATE = 101, WB Filter) 0 0 fIN = 100kHz, -6dBFS THD = -103.2dBc 65,536 Points -40 -60 -80 -100 -40 -60 -80 -100 -120 -120 -140 -140 -160 -160 0 0 200k 400k 600k 800k 1M 1.2M 1.4M 1.6M 1.
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ADS1675 www.ti.com SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 TYPICAL CHARACTERISTICS (continued) All specifications are at TA = –40°C to +85°C, AVDD = 5V, DVDD = 3V, fCLK = 32MHz, VREF = +3V, and RBIAS = 7.5kΩ, unless otherwise noted. |TOTAL HARMONIC DISTORTION| vs INPUT COMMON-MODE VOLTAGE 115 SIGNAL-TO-NOISE RATIO vs RBIAS 93.0 fIN = 10kHz fDATA = 4MSPS WB Filter 110 92.5 fCLK = 8MHz 92.0 SNR (dBc) |THD| (dBc) 91.5 AIN = -6dBFS 105 91.0 fCLK = 16MHz 90.5 90.0 89.
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ADS1675 SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) All specifications are at TA = –40°C to +85°C, AVDD = 5V, DVDD = 3V, fCLK = 32MHz, VREF = +3V, and RBIAS = 7.5kΩ, unless otherwise noted.
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ADS1675 www.ti.com SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 OVERVIEW The ADS1675 is a 24-bit, delta-sigma (ΔΣ) analog-to-digital converter (ADC). It provides high-resolution measurements of both ac and dc signals and features an advanced, multi-stage analog modulator with a programmable and flexible digital decimation filter. A dedicated START pin allows precise conversion control; toggle the pin to begin the conversion process.
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ADS1675 SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 www.ti.com NOISE PERFORMANCE The ADS1675 offers outstanding noise performance that can be optimized by adjusting the data rate. As the averaging is increased (thus reducing the data rate), the noise drops correspondingly. Table 1 shows the noise as a function of data rate for both the Low-Latency and the Wide-Bandwidth filter paths under the conditions shown. Table 1 lists some of the more common methods of specifying noise.
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ADS1675 www.ti.com SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 VOLTAGE REFERENCE INPUTS (VREFN, VREFP) CONVERSION START The voltage reference for the ADS1675 is the differential voltage between VREFP and VREFN: VREF = (VREFP – VREFN) (2) A high-quality reference voltage with the appropriate drive strength is essential for achieving the best performance from the ADS1675. Noise and drift on the reference degrade overall system performance.
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ADS1675 SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 www.ti.com DIGITAL FILTER LOW-LATENCY DIGITAL FILTER In ΔΣ ADCs, the digital filter has a critical influence on device performance. The digital filter sets the frequency response, data rate, bandwidth, and settling time. Choosing to optimize some of these features in a filter means that compromises must be made with other specifications. These tradeoffs determine the applications for which the device is best suited.
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ADS1675 www.ti.com SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 The second configuration is fast response. The DRATE[2:0] digital input pins select the data rate for the Fast Response Configuration, as shown in Table 5. When selected, this configuration provides a higher output data rate. The faster output data rate allows for more averaging by a post-processor within a given time interval to reduce noise.
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ADS1675 SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 www.ti.com It is important to note, however, that the absolute settling time of the Low-Latency path does not change when using the fast response configuration. Changes on the input signal during conversions after the initial settling require multiple cycles to fully settle. To help illustrate this requirement, consider a change on the inputs as shown in Figure 42, where START is assumed to have been taken high before the input voltage was changed.
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ADS1675 www.ti.com SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 Phase Response 20 0 -20 Magnitude (dB) The Low-Latency filter uses a multiple-stage, linear-phase digital filter. Linear phase filters exhibit constant delay time versus input frequency (also know as constant group delay). This feature of linear phase filters means that the time delay from any instant of the input signal to the corresponding same instant of the output data is constant and independent of the input signal frequency.
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ADS1675 SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 www.ti.com Settling Time The overall frequency response repeats at the modulator sampling rate, which is the same as the input clock frequency. Figure 46 shows the response with the fastest data rate selected (4 MSPS when fCLK = 32MHz). The Wide-Bandwidth filter fully settles before indicating data are ready for retrieval after the START pin is taken high, as shown in Figure 48.
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ADS1675 www.ti.com SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 OTRA, OTRD FUNCTIONS The ADS1675 provides two out-of-range pins (OTRD, OTRA) that can be used in feedback loops to set the dynamic range of the input signal. The OTRA signal is triggered when the analog input to the modulator exceeds the positive or the negative full-scale range, as shown in Figure 49. This signal is triggered synchronous to CLK and returns low when the input becomes within range.
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ADS1675 SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 www.ti.com USING LVDS OUTPUT SWINGS When the LVDS pin is set to '0', the ADS1675 outputs are LVDS TIA/EIA-644A compliant. The data out, shift clock, and data ready signals are output on the differential pairs of pins DOUT/DOUT, SCLK/SCLK, and DRDY/DRDY, respectively. The voltage on the outputs is centered on 1.2V and swings approximately 350mV differentially.
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ADS1675 www.ti.com SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 DATA FORMAT In the low-speed modes, the ADS1675 outputs 24 bits of data in twos complement format. A positive full-scale input produces an output code of 7FFFFFh, and the negative full-scale input produces an output code of 800000h. The output clips at these codes for signals that exceed full-scale. Table 8 summarizes the ideal output codes for different input signals.
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ADS1675 SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 www.ti.com ANALOG POWER DISSIPATION An external resistor connected between the RBIAS pin and the analog ground sets the analog current level, as shown in Figure 51. The current is inversely proportional to the resistor value. Figure 24 to Figure 26 (in the Typical Characteristics) show power and typical performance at values of RBIAS for different CLK frequencies.
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ADS1675 www.ti.com SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 +5V +3V 0.1mF 0.1mF 57 58 10mF 0.1mF 56 54 AVDD AGND AGND 53 52 51 50 49 AGND AVDD DVDD DGND DGND DVDD 1 AVDD DVDD 48 2 AGND DGND 47 0.1mF 10mF 3 AGND +5V 0.1mF 10mF 6 AGND ADS1675 7 AVDD 9 AGND 10 AGND 11 AVDD 12 AVDD DGND DGND DGND DGND DVDD DVDD DGND DGND DVDD DGND 17 18 19 20 23 24 25 26 27 31 0.1mF 10mF Figure 52.
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ADS1675 SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 www.ti.com APPLICATION INFORMATION To obtain the specified performance from the ADS1675, the following layout and component guidelines should be considered. 1. Power Supplies: The device requires two power supplies for operation: DVDD and AVDD. A very clean and stable AVDD supply is needed to achieve optimal performance from the device. For both supplies, use a 10mF tantalum capacitor, bypassed with a 0.
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ADS1675 www.ti.com SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 1kW 10nF +5V 0.1mF 10W OPA211 100W 1kW 100mF 10mF 0.1mF 1mF 63 62 OUT VIN +5V TRIM REF5030 0.1mF 64 3V 22mF 1mF 61 60 59 VREFP VREFP CAP2 VREFN VREFN CAP1 10W 4 AINN VINN Differential Inputs 10W VINP 100pF 750pF 5 AINP 100pF ADS1675 8 RBIAS 7.5kW 13 VCM 1 mF Figure 53. Basic Analog Signal Connection CF 100pF RF 249W +9V RG 249W CM 2.5V VIN+ CM 2.5V VIN- + - VINN + VINP THS4503 RG 249W CM 2.
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ADS1675 SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 www.ti.com CF 100pF Signal Source RG 243W RS 50W RT 59W VIN CM 2.5V CM 2.5V RS 50W CM 2.5V RG 243W RF 249W +9V + - RT 59W CM 2.5V - VINN + VINP THS4503 CM -4V 2.5V RF 249W CF 100pF Figure 55.
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ADS1675 www.ti.com SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 REVISION HISTORY NOTE: Page numbers for previous revisions may differ form page numbers in the current version. Changes from Revision C (September 2009) to Revision D Page • Changed 115dB to 86dB in second paragraph of Description section .................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS1675IPAGR Package Package Pins Type Drawing TQFP PAG 64 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1500 330.0 24.4 Pack Materials-Page 1 13.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.0 1.5 16.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1675IPAGR TQFP PAG 64 1500 367.0 367.0 45.
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MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.