Datasheet

Biasing
RBIAS
CAP1
CAP2
AINP
AINN
VCM
CS
LVDS
OTRA
LL_CONFIG
ADS1675
SCLK_SEL
DS
Modulator
DVDD
DGND
AGND
AVDD
VREFP VREFN
Dual
Path
Filter
Low-LatencyFilter
Wide-BandwidthFilter
CMOS-and
LVDS-
Compatible
Serial
Interface
and
Control
V
IN
V
REF
SCLK, SCLK
DOUT, DOUT
DRDY, DRDY
CLK
START
PDWN
S
S
DRATE[2:0]
OTRD
FPATH
CLK
PLL
3x
ADS1675
www.ti.com SBAS416D –DECEMBER 2008–REVISED AUGUST 2010
OVERVIEW
The ADS1675 is a 24-bit, delta-sigma (ΔΣ) A dedicated START pin allows precise conversion
analog-to-digital converter (ADC). It provides control; toggle the pin to begin the conversion
high-resolution measurements of both ac and dc process. The ADS1675 is configured by setting the
signals and features an advanced, multi-stage analog appropriate I/O pins—there are no registers to
modulator with a programmable and flexible digital program. Data are retrieved over a serial interface
decimation filter. that can support either CMOS or LVDS voltage
levels. In addition, the standard CMOS serial
Figure 35 shows a block diagram of the ADS1675.
interface can be internally or externally clocked. This
The modulator measures the differential input signal
flexibility allows direct connection to a wide range of
V
IN
= (AINP – AINN) against the differential reference
digital hosts including DSPs, FPGAs, and
V
REF
= (VREFP – VREFN). The digital filter receives
microcontrollers. All data rates are available only
the modulator signal and processes it through the
using the LVDS mode interface.
user-selected path. The Low-Latency path settles
quickly, and is ideal when using a multiplexer or when A detection circuit monitors the conversions to
measuring large transients. The Wide-Bandwidth path indicate when the inputs are out-of-range for an
provides outstanding frequency response with very extended duration. A power-down pin (PDWN) shuts
low passband ripple, a steep transition band, and off all circuitry when the ADS1675 is not in use.
large stop band attenuation. This path is well-suited
The device offers two speed modes with distinct
for applications that require high-resolution
interfaces, resolution, and feature set. The
measurements of high-frequency ac signal content.
high-speed mode is enabled by setting DRATE[2:0] to
either 100 or 101. The rest of the DRATE
configurations enable the low-speed mode.
Figure 35. Block Diagram
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): ADS1675