Datasheet

ADS1675
SBAS416D –DECEMBER 2008–REVISED AUGUST 2010 www.ti.com
DIGITAL FILTER LOW-LATENCY DIGITAL FILTER
In ΔΣ ADCs, the digital filter has a critical influence The Low-Latency (LL) filter provides a fast settling
on device performance. The digital filter sets the response targeted for applications that need
frequency response, data rate, bandwidth, and high-precision measurements with minimal latency. A
settling time. Choosing to optimize some of these good example of this type of application is a
features in a filter means that compromises must be multiplexer that measures multiple inputs. The faster
made with other specifications. These tradeoffs the ADC settles, the faster the measurement can
determine the applications for which the device is complete and the multiplexer can advance to the next
best suited. input.
The ADS1675 offers two digital filters on-chip, and The ADS1675 LL filter supports two configurations to
allows the user to direct the output data from the help optimize performance for these types of
modulator to either the Wide-Bandwidth or applications.
Low-Latency filter. These filters allow the user to use
The LL_CONFIG input pin selects the configuration,
one converter design to address multiple applications.
as shown in Table 3. Be sure to strobe the START
The Low-Latency path filter has minimal latency or
pin after changing the configuration. If a conversion is
settling time. This reduction is achieved by reducing
in process during a configuration change, the output
the bandwidth of the filter. This path is ideal for
data for that conversion are not valid and should be
measurements with large, quick changes on the
discarded.
inputs (for example, when using a multiplexer). The
Low-Latency characteristic allows the user to cycle
Table 3. Low-Latency Pin Configurations
through the multiplexer at high speeds.
LOW-LATENCY
The other path provides a filter with excellent
LL_CONFIG PIN CONFIGURATION
frequency response characteristics. The passband
0 Single-cycle settling
ripple is extremely small, the transition band is very
1 Fast response
steep, and there is large stop band attenuation.
These characteristics are needed for high-resolution
The first configuration is single-cycle settling. As the
measurements of ac signals. The tradeoff here is that
name implies, this configuration allows for the filter to
settling time increases; for signal processing,
completely settle in one conversion cycle; there is no
however, this increase is not generally a critical
need to discard data. Each data output is comprised
concern.
of information taken during only the previous
conversion. The DRATE[2:0] digital input pins select
The FPATH digital input pin sets the filter path
the data rate for the Single-Cycle Settling
selection, as shown in Table 2. Note that the START
configuration, as shown in Table 4. Note that the
pin must be strobed after a change to the filter path
START pin must be strobed after a change to the
selection or data rate. If a conversion is in process
data rate. If a conversion is in process during a data
during a filter path or data rate change, the output
rate change, the output data for that conversion are
data are not valid and should be discarded.
not valid and should be discarded.
Table 2. ADS1675 Filter Path Selection
blank
FPATH PIN SELECTED FILTER PATH
blank
1 Low-Latency path
0 Wide-Bandwidth path
Table 4. Low-Latency Data Rates with Single-Cycle Settling Configuration
DRATE[2:0] DATA RATE (kSPS) SETTLING TIME, t
SETTLE-LL
–3dB BANDWIDTH (kHz)
(1)
000 57.80 17.375ms 556t
CLK
54
001 107.53 9.375ms 300t
CLK
109
010 188.68 5.375ms 172t
CLK
208
011 277.78 3.625ms 116t
CLK
344
(1) The input signal aliases when its frequency exceeds f
DATA
/2, in accordance with the Nyquist theorem.
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