Datasheet

t
DRDY-SCS
SETTLE-LL
=
t +1t +t
CLKDR CLK
START
CLK
t
START_CLKR
DRDY
SCS
DRDY
FR
t
SETTLE-LL
t
CLKDR
t
DRDY-FR
ADS1675
www.ti.com SBAS416D –DECEMBER 2008–REVISED AUGUST 2010
Settling Time
The second configuration is fast response. The
DRATE[2:0] digital input pins select the data rate for
The settling time in absolute time (ms) is the same for
the Fast Response Configuration, as shown in
both configurations of the Low-Latency filter, as
Table 5. When selected, this configuration provides a
shown in Table 4 and Table 5. The difference
higher output data rate. The faster output data rate
between the configurations is seen with the timing of
allows for more averaging by a post-processor within
the conversions after the filter has settled from a
a given time interval to reduce noise. It also provides
pulse on the START pin.
a faster indication of changes on the inputs when
monitoring quickly-changing signals (for example, in a Figure 38 illustrates the response of both
control loop application). configurations on approximately the same time scale
in order to highlight the differences. With the
Table 5. Low-Latency Data Rates with single-cycle settling configuration, each conversion
Fast-Response Configuration
fully settles; in other words, the conversion period
t
DRDY-SCS
= t
SETTLE-LL
. The benefit of this configuration
DATA –3dB
is its simplicity—the ADS1675 functions similar to a
DRATE RATE SETTLING TIME, BANDWIDTH
[2:0] (kSPS) t
SETTLE-LL
(kHz)
successive-approximation register (SAR) converter
and there is no need to consider discarding
000 125 17.375ms 556t
CLK
54
partially-settled data because each conversion is fully
001 250 9.375ms 300t
CLK
109
settled.
010 500 5.375ms 172t
CLK
208
With the fast response configuration, the data rate for
011 1000 3.625ms 116t
CLK
344
conversions after initial settling is faster; that is, the
100 2000 2.76ms 265t
LSCLK
350
conversion time is less than the settling:
101 4000 2.385ms 229t
LSCLK
355
t
DRDY-FR
< t
SETTLE-LL
. One benefit of this configuration
is a faster response to changes on the inputs,
1. The input signal aliases when its frequency
because data are supplied at a faster rate. Another
exceeds f
DATA
/2, in accordance with the Nyquist
advantage is better support for post-processing. For
theorem.
example, if multiple readings are averaged to reduce
2. For high-speed mode, the first data are unsettled.
noise, the higher data rate of the fast response
configuration allows this averaging to happen in less
time than it requires with the single-cycle settling
filter. A third benefit is the ability to measure higher
input frequencies without aliasing as a result of the
higher data rate.
NOTE: DRDY
SCS
is the DRDY output with the Low-Latency single-cycle settling configuration. DRDY
FR
is the DRDY output with the
Low-Latency fast-response settling configuration.
Figure 38. Low-Latency Single-Cycle Settling and Fast-Response Configuration Conversion Timing
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