Datasheet

OTRA
(Low-SpeedMode)
DRDY
CLK
AIN
3V
SCLK
(High-SpeedMode)
OTRA
(High-Speed Mo e)d
ADS1675
www.ti.com SBAS416D –DECEMBER 2008–REVISED AUGUST 2010
OTRA, OTRD FUNCTIONS The high-speed modes (DRATE = 100, 101) are
supported in high-speed LVDS interface mode only.
The ADS1675 provides two out-of-range pins (OTRD,
The state of the LVDS pin and the SCLK_SEL are
OTRA) that can be used in feedback loops to set the
ignored. In these two modes, an on-chip PLL is used
dynamic range of the input signal.
to multiply the input clock (CLK) by three, to be used
for the serial interface. This high-speed clock enables
The OTRA signal is triggered when the analog input
all 23-bit output data to be shifted out at the high data
to the modulator exceeds the positive or the negative
rate. The DRDY pulse in this case is three serial
full-scale range, as shown in Figure 49. This signal is
clocks wide. The on-chip PLL can lock to input clocks
triggered synchronous to CLK and returns low when
ranging from 8MHz to 32MHz. To conserve power,
the input becomes within range. The falling edge of
the PLL is enabled only in the high-speed modes.
OTRA is synchronized with the falling edge of DRDY.
After power up as well as after the CLK signal is
OTRA can be used in feedback loops to correct input
issued, if the CLK frequency is changed, and when
over range conditions quicker instead of waiting for
switching from low-speed mode to high-speed mode,
the digital filter to settle.
the PLL needs at least t
LPLLSTL
to lock on and
The OTRD function is triggered when the output code
generate a proper LVDS serial shift clock. Switching
of the digital filter exceeds the positive or negative
among the high-speed modes does not require the
full-scale range. OTRD goes high on the rising edge
user to wait for the PLL to lock. While the PLL is
of DRDY. When the digital output code returns within
locking on, DOUT and SCLK are held low. After the
the full-scale range, OTRD returns low on the next
PLL has locked on, the SCLK pin outputs a
rising edge of DRDY. OTRD can also be used when
continuous clock that is three times the frequency of
small out-of-range input glitches must be ignored.
CLK. The device gives out a DRDY pulse (regardless
of the status of the START signal) to indicate that the
OTRA can be used in feedback loops to correct input
lock is complete. Disregard the data associated with
over-range conditions quickly.
this DRDY pulse. After this DRDY pulse, it is
recommended that the user toggle the start signal
SERIAL INTERFACE
before starting to capture data.
The ADS1675 offers a flexible and easy-to-use,
The ADS1675 is entirely controlled by pins; there are
read-only serial interface designed to connect to a
no registers to program. Connect the I/O pins to the
wide range of digital processors, including DSPs,
appropriate level to set the desired function.
microcontrollers, and FPGAs. In the low-speed
Whenever changing the digital I/O pins that control
modes (DRATE = 000 to 011) the ADS1675 serial
the ADS1675, be sure to issue a START pulse
interface can be configured to support either standard
immediately after the change in order to latch the new
CMOS voltage swings or low-voltage differential
values.
swings (LVDS). In addition, when using standard
CMOS voltage swings, SCLK can be internally or
externally generated.
Figure 49. OTRA Signal Trigger
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