Datasheet

ADS1675
SBAS416D –DECEMBER 2008–REVISED AUGUST 2010 www.ti.com
USING LVDS OUTPUT SWINGS The DRDY pulse is the primary indicator from the
ADS1675 that data are available for retrieval. Table 5
When the LVDS pin is set to '0', the ADS1675
and Table 6 only give approximate values for settling
outputs are LVDS TIA/EIA-644A compliant. The data
time after a START signal. The rising edge of DRDY
out, shift clock, and data ready signals are output on
should be used as an indicator to start the data
the differential pairs of pins DOUT/DOUT,
capture with the serial shift clock.
SCLK/SCLK, and DRDY/DRDY, respectively. The
voltage on the outputs is centered on 1.2V and
SERIAL SHIFT CLOCK (SCLK, SCLK,
swings approximately 350mV differentially. For more
SCLK_SEL)
information on the LVDS interface, refer to the
document Low-Voltage Differential Signaling (LVDS)
The serial shift clock SCLK is used to shift out the
Design Notes (literature number SLLA014) available
conversion data, MSB first, onto the Data Output
for download at www.ti.com.
pins. Either an internally- or externally-generated shift
clock can be selected using the SCLK_SEL pin. If
When using LVDS, SCLK must be internally
SCLK_SEL is set to '0', a free-running shift clock is
generated. The states of SCLK_SEL pin is ignored.
generated internally from the master clock and
Do not leave these pins floating; they must be tied
outputs on the SCLK and SCLK pins. The LVDS pin
high or low.
determines if the output voltages are CMOS or LVDS.
If SCLK_SEL is set to '1' and LVDS is set to '1', the
USING CMOS OUTPUT SWINGS
SCLK pin is configured as an input to accept an
externally-generated shift clock. In this case, the
When the LVDS pin is set to '1', the ADS1675
SCLK pin enters a high-impedance state. When
outputs are CMOS-compliant and swing from rail to
SCLK_SEL is set to '0', the SCLK and SCLK pins are
rail. The data out and data ready signals are output
configured as outputs, and the shift clock is
on the differential pairs of pins DOUT/DOUT and
generated internally using the master clock input
DRDY/DRDY, respectively. Note that these are the
(CLK).
same pins used to output LVDS signals when the
LVDS pin is set to '0'. DOUT and DRDY are
When LVDS signal swings are used, the shift clock is
complementary outputs provided for convenience.
automatically generated internally regardless of the
When not in use, these pins should be left floating.
state of SCLK_SEL. In this case, SCLK_SEL cannot
be left floating; it must be tied high or low.
See the Serial Shift Clock section for a description of
the SCLK and SCLK pins.
Table 7 summarizes the supported serial clock
configurations for the ADS1675.
DATA OUTPUT (DOUT, DOUT)
Table 7. Supported Serial Clock Configurations
Data are output serially from the ADS1675, MSB first,
on the DOUT and DOUT pins. When LVDS signal
DIGITAL OUTPUTS SHIFT CLOCK (SCLK)
swings are used, these two pins act as a differential
LVDS Internal
pair to produce the LVDS-compatible differential
Internal (SCLK_SEL = '0')
output signal. When CMOS signal swings are used,
CMOS
External (SCLK_SEL = '1')
the DOUT pin is the complement of DOUT. If DOUT
is not used, it should be left floating.
CHIP SELECT (CS)
DATA READY (DRDY, DRDY)
The chip select input (CS) allows multiple devices to
Data ready for retrieval are indicated on the DRDY
share a serial bus. When CS is inactive (high), the
and DRDY pins. When LVDS signal swings are used,
serial interface is reset and the data output pins
these two pins act as a differential pair to produce the
DOUT and DOUT enter a high-impedance state.
LVDS-compatible differential output signal. When
SCLK is internally generated; the SCLK and SCLK
CMOS signal swings are used, the DRDY pin is the
output pins also enter a high-impedance state when
complement of DRDY. If one of the data ready pins is
CS is inactive. The DRDY and DRDY outputs are
not used when CMOS swings are selected, it should
always active, regardless of the state of the CS
be left floating.
output. CS may be permanently tied low when the
outputs do not share a bus.
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