Datasheet

+V
2 1
REF
-
23
-V
2 1
REF
-
23
-V
REF
2
2 1-
23
23
( )
<
START
1
ADS1675
1
CLK
DRDY DRDY
1
START
CLK
START
2
ADS1675
2
CLK
DRDY DRDY
2
START
CLK
DRDY
1
DRDY
2
t
SETTLE
ADS1675
www.ti.com SBAS416D –DECEMBER 2008–REVISED AUGUST 2010
DATA FORMAT Measuring high-frequency, large amplitude signals
requires tight control of clock jitter. The uncertainty
In the low-speed modes, the ADS1675 outputs 24
during sampling of the input from clock jitter limits the
bits of data in twos complement format. A positive
maximum achievable SNR. This effect becomes more
full-scale input produces an output code of 7FFFFFh,
pronounced with higher frequency and larger
and the negative full-scale input produces an output
magnitude inputs. Fortunately, the ADS1675
code of 800000h. The output clips at these codes for
oversampling topology reduces clock jitter sensitivity
signals that exceed full-scale. Table 8 summarizes
over that of Nyquist rate converters, such as pipeline
the ideal output codes for different input signals.
and SAR converters, by at least a factor of √8.
When the input is positive out-of-range, exceeding
the positive full-scale value of V
REF
, the output clips to
SYNCHRONIZING MULTIPLE ADS1675s
all 7FFFFFh. Likewise, when the input is negative
out-of-range by going below the negative full-scale
The START pin should be applied at power-up and
value of –V
REF
, the output clips to 800000h.
resets the ADS1675 filters. START begins the
conversion process, and the START pin enables
Table 8. Ideal Output Code vs Input Signal
simultaneous sampling with multiple ADS1675s in
multichannel systems. All devices to be synchronized
INPUT SIGNAL
must use a common CLK input.
V
IN
= (AINP – AINN) IDEAL OUTPUT CODE
≥ V
REF
7FFFFFh
It is recommended that the START pin be aligned to
the falling edge of CLK to ensure proper
000001h
synchronization because the START signal is
internally latched by the ADS1675 on the rising edge
0 000000h
of CLK.
With the CLK inputs running, pulse START on the
FFFFFFh
falling edge of CLK, as shown in Figure 50.
Afterwards, the converters operate synchronously
with the DRDY outputs updating simultaneously. After
8000000h
synchronization, DRDY is held high until the digital
filter has fully settled.
1. Excludes effects of noise, INL, offset and gain
errors.
In the high-speed modes, the ADS1675 has 23 bits of
resolution. The 24th bit in these modes is held low.
CLOCK INPUT (CLK)
The ADS1675 requires an external clock signal to be
applied to the CLK input pin. The sampling of the
modulator is controlled by this clock signal. As with
any high-speed data converter, a high-quality clock is
essential for optimum performance. Crystal clock
oscillators are the recommended CLK source; other
sources, such as frequency synthesizers, are usually
inadequate. Make sure to avoid excess ringing on the
CLK input; keep the trace as short as possible.
For best performance, the CLK duty cycle should be
very close to 50%. The rise and fall times of the clock
should be less than 1ns and clock amplitude should
be equal to AVDD.
Figure 50. Synchronizing Multiple Converters
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