Datasheet

t
LSCLKDC
DRDY
MSB
LSB MSB
D UTO
S LKC
t
LSCLKDR
t
LDOPD
t
LDRPW
t
LSCLK
CLK
SCLK
START
DRDY
t
STCLK
t
LSCLKDR
t
LSCLK
t
LCLKSCLK
t
SETTLE
t
LPLLSTL
t
CLK
t
SETTLE
ADS1675
www.ti.com SBAS416D –DECEMBER 2008–REVISED AUGUST 2010
TIMING CHARACTERISTICS
(1) High-speed LVDS valid only for DRATE = 100 and DRATE = 101.
(2) Timing shown is the single-end version of the LVDS signal pairs.
Figure 1. High-Speed LVDS Data Retrieval Timing
TIMING REQUIREMENTS: High-Speed LVDS
At T
A
= –40°C to +85°C, and DVDD = 2.85V to 3.15V.
SYMBOL DESCRIPTION MIN TYP MAX UNIT
t
LDRPW
DRDY pulse width 2 4 t
LSCLKs
t
LSCLKDR
SCLK to DRDY delay 2 3 ns
t
LDOPD
Valid data delay time from serial shift clock 1.5 2.5 ns
t
LSCLK
Period of LVDS serial shift clock (SCLK) 0.33 t
CLKs
t
LSCLKDC
Shift clock duty cycle 47 53 %
t
CLK
CLK period (1/f
CLK
) 31.25 ns
t
LCLKSCLK
Delay from rising edge of CLK to rising edge of SCLK 13 20 ns
t
LPLLSTL
PLL settling time 80 ms
t
STCLK
Setup time, rising edge of START to falling edge of CLK –3 3 ns
t
SETTLE
Digital filter settling time See Table 5 and Table 6
Figure 2. PLL Timing
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): ADS1675