Datasheet

CLK
DRDY
t
CLK
t
LSCLK
SCLK
internal
t
LDOPD
t
DRSCLK
DOUT
MSB LSB
t
LDRPW
t
LCLKDR
CS
t
SPWH
t
DC
ADS1675
SBAS416D –DECEMBER 2008–REVISED AUGUST 2010 www.ti.com
Figure 3. Low-Speed Mode Data Retrieval Timing with Internal SCLK (SCLK_SEL = 0)
TIMING REQUIREMENTS: Internal SCLK
At T
A
= –40°C to +85°C, and DVDD = 2.85V to 3.15V.
SYMBOL DESCRIPTION MIN TYP MAX UNIT
t
DC
CLK duty cycle 47 50 53 %
t
SPWH
SCLK pulse width high 15.6 ns
t
CLK
CLK period (1/f
CLK
) 31.25 ns
t
CLKDR
CLK to DRDY delay 23 30 ns
t
LDRPW
DRDY pulse width 1 t
CLK
t
DRSCLK
Internal SCLK Rising to DRDY active edge 2.2 4.4 ns
t
LSCLK
Internally-generated SCLK rising edge to DRDY rising edge 1 t
CLK
t
LDOPD
Rising edge of SCLK to new valid data output (propagation delay) 1.9 2.8 ns
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