Datasheet

CLK
DRDY
t
LSCLK
SCLK
EXTERNAL
t
LDRPW
t
CLKDR
t
CSSC
t
CSFDO
t
SPW
t
SPW
t
LDOPD
t
CSRDO
DOUT
CS
(1)
MSB
LSB
t
CLK
t
LSCLKDR
Hi-Z
START
DRDY
CLK
t
START_CLKR
t
SETTLE
t
START
t
CLKDR
ADS1675
www.ti.com SBAS416D –DECEMBER 2008–REVISED AUGUST 2010
(3) CS may be tied low.
Figure 4. Low-Speed Mode Data Retrieval Timing with External SCLK (SCLK_SEL = 1)
TIMING REQUIREMENTS: External SCLK
At T
A
= –40°C to +85°C, and DVDD = 2.85V to 3.15V.
SYMBOL DESCRIPTION MIN TYP MAX UNIT
t
CLK
CLK period (1/f
CLK
) 31.25 ns
t
CLKDR
CLK to DRDY delay 23 29 ns
t
LDRPW
DRDY pulse width 1 t
CLK
t
CSSC
CS active low to first Shift Clock (setup time) 5 ns
t
LSCLK
SCLK period (1/f
SCLK
) 25 ns
t
SPW
SCLK high or low pulse width 12 ns
t
LDOPD
Rising edge of SCLK to new valid data output (propagation delay) 10.5 15 ns
t
LSCLKDR
Setup time of DRDY rising after SCLK falling edge 3 t
CLK
t
CSRDO
CS rising edge to DOUT 3-state 8 ns
Figure 5. START Timing
TIMING REQUIREMENTS: START
At T
A
= –40°C to +85°C, and DVDD = 2.85V to 3.15V.
SYMBOL DESCRIPTION MIN TYP MAX UNIT
t
START_CLKR
Setup time, rising edge of START to rising edge of CLK 0.5 t
CLK
t
START
Start pulse width 2 t
CLK
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