Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) Internal VQFN 48

ADS4122, ADS4125

ADS4142, ADS4145

www.ti.com

SBAS520A –FEBRUARY 2011– REVISED MARCH 2011

14-/12-Bit, 65/125MSPS, Ultralow-Power ADC

Check for Samples: ADS4122, ADS4125, ADS4142, ADS4145

FEATURES

DESCRIPTION

The ADS412x/4x are lower sampling speed variants

• Ultralow Power with 1.8V Single Supply:

of the ADS41xx family of analog-to-digital converters

– 103mW Total Power at 65MSPS

(ADCs). These devices use innovative design

– 153mW Total Power at 125MSPS

techniques to achieve high dynamic performance,

while consuming extremely low power at 1.8V supply.

• High Dynamic Performance:

The devices are well-suited for multi-carrier, wide

– SNR: 72.2dBFS at 170MHz

bandwidth communications applications.

– SFDR: 81dBc at 170MHz

The ADS412x/4x have fine gain options that can be

• Dynamic Power Scaling with Sample Rate

used to improve SFDR performance at lower

• Output Interface:

full-scale input ranges, especially at high input

frequencies. They include a dc offset correction loop

– Double Data Rate (DDR) LVDS with

that can be used to cancel the ADC offset. At lower

Programmable Swing and Strength

sampling rates, the ADC automatically operates at

– Standard Swing: 350mV

scaled down power with no loss in performance.

– Low Swing: 200mV

The ADS412x/4x are available in a compact QFN-48

– Default Strength: 100Ω Termination

pacakge and are specified over the industrial

– 2x Strength: 50Ω Termination

temperature range (–40°C to +85°C).

– 1.8V Parallel CMOS Interface Also

Supported

• Programmable Gain up to 6dB for SNR/SFDR

Trade-Off

• DC Offset Correction

• Supports Low Input Clock Amplitude Down To

200mV

• Package: QFN-48 (7mm × 7mm)

ADS412x/ADS414x Family Comparison

WITH ANALOG INPUT BUFFERS

FAMILY 65MSPS 125MSPS 160MSPS 250MSPS 200MSPS 250MSPS

ADS412x

ADS4122 ADS4125 ADS4126 ADS4129 — ADS41B29

12-Bit Family

ADS414x

ADS4142 ADS4145 ADS4146 ADS4149 — ADS41B49

14-Bit Family

9-Bit — — — — — ADS58B19

11-Bit — — — — ADS58B18 —

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments Incorporated.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (81 pages)

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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com 14-/12-Bit, 65/125MSPS, Ultralow-Power ADC Check for Samples: ADS4122, ADS4125, ADS4142, ADS4145 FEATURES DESCRIPTION • The ADS412x/4x are lower sampling speed variants of the ADS41xx family of analog-to-digital converters (ADCs). These devices use innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8V supply.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. VALUE UNIT Supply voltage range, AVDD –0.3 to 2.1 V Supply voltage range, DRVDD –0.3 to 2.1 V Voltage between AGND and DRGND –0.3 to 0.3 V 0 to 2.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS Over operating free-air temperature range, unless otherwise noted. ADS4122/5, ADS4142/5 MIN TYP MAX UNIT SUPPLIES AVDD Analog supply voltage 1.7 1.8 1.9 V DRVDD Digital supply voltage 1.7 1.8 1.9 V ANALOG INPUTS Differential input voltage range (1) 2 VPP VCM ± 0.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS: ADS4122/ADS4125 Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, and DDR LVDS interface, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.8V.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS: ADS4142/ADS4145 Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, and DDR LVDS interface, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.8V.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS: GENERAL Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, and 0dB gain, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.8V.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com DIGITAL CHARACTERISTICS Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, and 50% clock duty cycle, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.8V. ADS4122, ADS4125, ADS4142, ADS4145 PARAMETER TEST CONDITIONS MIN RESET, SCLK, SDATA, and SEN support 1.8V and 3.3V CMOS logic levels 1.3 OE only supports 1.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com ADS414x, ADS412x Pin Assignments (LVDS Mode) PIN NAME PIN NUMBER # OF PINS FUNCTION AVDD 8, 18, 20, 22, 24, 26 6 I 1.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com ADS414x, ADS412x Pin Assignments (CMOS Mode) 14 PIN NAME PIN NUMBER # OF PINS FUNCTION AVDD 8, 18, 20, 22, 24, 26 6 I 1.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 AVDD www.ti.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com TIMING CHARACTERISTICS Dn_Dn + 1_P Logic 0 VODL Logic 1 VODH Dn_Dn + 1_M VOCM GND (1) With external 100Ω termination. Figure 7. LVDS Output Voltage Levels TIMING REQUIREMENTS: LVDS and CMOS Modes (1) Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, sampling frequency = 125 MSPS, sine wave input clock, CLOAD = 5pF (2), and RLOAD = 100Ω (3), unless otherwise noted.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com TIMING REQUIREMENTS: LVDS and CMOS Modes(1) (continued) Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, sampling frequency = 125 MSPS, sine wave input clock, CLOAD = 5pF(2), and RLOAD = 100Ω(3), unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.7V to 1.9V.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com Table 2. LVDS Timing Across Sampling Frequencies SAMPLING FREQUENCY (MSPS) SETUP TIME (ns) MIN HOLD TIME (ns) TYP MAX MIN TYP 65 5.5 6.5 0.35 0.60 80 4.50 5.20 0.35 0.60 MAX Table 3. CMOS Timing Across Sampling Frequencies (Low Latency Enabled) TIMING SPECIFIED WITH RESPECT TO OUTPUT CLOCK SAMPLING FREQUENCY (MSPS) MIN TYP 65 6.5 80 5.4 tSETUP (ns) tHOLD (ns) MAX MIN TYP 7.5 6.5 6.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com CLKM Input Clock CLKP tPDI CLKOUTP Output Clock CLKOUTM tSU Output Dn_Dn + 1_P Data Pair Dn_Dn + 1_M tSU tH Dn (1) Dn + 1 tH (1) (1) Dn = bits D0, D2, D4, etc. Dn + 1 = Bits D1, D3, D5, etc. Figure 9. LVDS Mode Timing CLKM Input Clock CLKP tPDI Output Clock CLKOUT tSU Output Data Dn tH Dn (1) CLKM Input Clock CLKP tSTART tDV Output Data Dn Dn (1) Dn = bits D0, D1, D2, etc. Figure 10.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com DEVICE CONFIGURATION The ADS412x/4x have several modes that can be configured using a serial programming interface, as described in Table 5, Table 6, and Table 7. In addition, the devices have two dedicated parallel pins for quickly configuring commonly used functions. The parallel pins are DFS (analog 4-level control pin) and OE (digital control pin).
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com SERIAL INTERFACE The analog-to-digital converter (ADC) has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins. Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA are latched at every falling edge of SCLK when SEN is active (low).
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com Serial Register Readout The serial register readout function allows the contents of the internal registers to be read back on the OVR_SDOUT pin. This readback may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. After power-up and device reset, the OVR_SDOUT pin functions as an over-range indicator pin by default.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com RESET TIMING CHARACTERISTICS Power Supply AVDD, DRVDD t1 RESET t3 t2 SEN NOTE: A high pulse on the RESET pin is required in the serial interface mode in case of initialization through hardware reset. For parallel interface operation, RESET must be permanently tied high. Figure 14.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com SERIAL REGISTER MAP Table 8 summarizes the functions supported by the serial interface. Table 8.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com Register Address 25h (Default = 00h) 7 6 5 4 GAIN Bits[7:4] 3 2 1 DISABLE GAIN 0 TEST PATTERNS GAIN: Gain programmability These bits set the gain programmability in 0.5dB steps. 0000 0001 0010 0011 0100 0101 0110 Bit 3 = = = = = = = 0dB gain (default after reset) 0.5dB gain 1.0dB gain 1.5dB gain 2.0dB gain 2.5dB gain 3.0dB gain 0111 1000 1001 1010 1011 1100 = = = = = = 3.5dB gain 4.0dB gain 4.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com Register Address 26h (Default = 00h) 7 6 0 5 0 4 0 3 0 0 2 1 0 0 LVDS CLKOUT STRENGTH LVDS DATA STRENGTH Bits[7:2] Always write '0' Bit 1 LVDS CLKOUT STRENGTH: LVDS output clock buffer strength This bit determines the external termination to be used with the LVDS output clock buffer.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com Register Address 41h (Default = 00h) 7 6 LVDS CMOS Bits[7:6] 5 4 CMOS CLKOUT STRENGTH 3 EN CLKOUT RISE 2 1 CLKOUT RISE POSN 0 EN CLKOUT FALL LVDS CMOS: Interface selection These bits select the interface.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com Register Address 43h (Default = 00h) 7 6 5 4 3 2 1 0 PDN GLOBAL 0 PDN OBUF 0 0 EN LVDS SWING Bit 0 Always write '0' Bit 6 PDN GLOBAL: Power-down 0 This bit sets the state of operation. 0 = Normal operation 1 = Total power down; the ADC, internal references, and output buffers are powered down; slow wake-up time.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com Register Address BFh (Default = 00h) 7 6 5 4 3 2 OFFSET PEDESTAL Bits[7:2] 1 0 0 0 OFFSET PEDESTAL These bits set the offset pedestal. When the offset correction is enabled, the final converged value after the offset is corrected is the ADC mid-code value. A pedestal can be added to the final converged value by programming these bits.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com Register Address CFh (Default = 00h) 7 6 FREEZE OFFSET CORR 0 Bit 7 5 4 3 2 OFFSET CORR TIME CONSTANT 1 0 0 0 FREEZE OFFSET CORR This bit sets the freeze offset correction. 0 = Estimation of offset correction is not frozen (bit EN OFFSET CORR must be set) 1 = Estimation of offset correction is frozen (bit EN OFFSET CORR must be set).
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4122 At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. FFT FOR 20MHz INPUT SIGNAL FFT FOR 170MHz INPUT SIGNAL 0 0 SFDR = 85.1dBc SNR = 71.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4122 (continued) At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4122 (continued) At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4122 (continued) At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4122 (continued) At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4125 At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. FFT FOR 20MHz INPUT SIGNAL FFT FOR 170MHz INPUT SIGNAL 0 0 SFDR = 86.9dBc SNR = 71.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4125 (continued) At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4125 (continued) At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4125 (continued) At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4125 (continued) At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4142 At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. FFT FOR 20MHz INPUT SIGNAL FFT FOR 170MHz INPUT SIGNAL 0 0 SFDR = 83.4dBc SNR = 74.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4142 (continued) At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4142 (continued) At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4142 (continued) At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4142 (continued) At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4145 At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. FFT FOR 20MHz INPUT SIGNAL FFT FOR 170MHz INPUT SIGNAL 0 0 SFDR = 86dBc SNR = 74dBFS SINAD =73.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4145 (continued) At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4145 (continued) At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4145 (continued) At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4145 (continued) At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: COMMON At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: CONTOUR At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: CONTOUR (continued) At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: CONTOUR (continued) At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com APPLICATION INFORMATION THEORY OF OPERATION The ADS412x/4x are lower sampling speed members of the ADS41xx family of ultralow power analog-to-digital converters (ADCs). The conversion process is initiated by a rising edge of the external input clock and the analog input signal is sampled.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com In the ADS412x/4x, the R-C component values have been optimized while supporting high input bandwidth (550MHz). However, in applications where very high input frequency support is not required, filtering of the glitches can be improved further with an external R-C-R filter; see Figure 104 and Figure 105).
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com Driving Circuit Two example driving circuit configurations are shown in Figure 104 and Figure 105—one optimized for low bandwidth (tlow input frequencies) and the other one for high bandwidth to support higher input frequencies. In Figure 104, an external R-C-R filter with 3.3pF is used to help absorb sampling glitches.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and good performance is obtained for high-frequency input signals. An additional termination resistor pair may be required between the two transformers, as shown in Figure 104 and Figure 105.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com CLOCK INPUT The ADS412x/4x clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM using internal 5kΩ resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave clock or ac-coupling for LVPECL and LVDS clock sources.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com DIGITAL FUNCTIONS AND LOW LATENCY MODE The device has several useful digital functions such as test patterns, gain, and offset correction. All of these functions require extra clock cycles for operation and increase the overall latency and power of the device. Alternately, the device has a low-latency mode in which the raw ADC output is routed to the output data pins with a latency of 10 clock cycles.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com OFFSET CORRECTION The ADS412x/4x has an internal offset corretion algorithm that estimates and corrects dc offset up to ±10mV. The correction can be enabled using the EN OFFSET CORR serial register bit. Once enabled, the algorithm estimates the channel offset and applies the correction every clock cycle. The time constant of the correction loop is a function of the sampling clock frequency.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com POWER DOWN The ADS412x/4x has three power-down modes: power-down global, standby, and output buffer disable. Power-Down Global In this mode, the entire chip (including the ADC, internal reference, and the output buffers) are powered down, resulting in reduced total power dissipation of about 10mW. The output buffers are in a high-impedance state.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com DIGITAL OUTPUT INFORMATION The ADS412x/4x provide either 14-bit data or 12-bit data, respectively, and an output clock synchronized with the data. Output Interface Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. They can be selected using the LVDS CMOS serial interface register bit or using the DFS pin.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com Even data bits (D0, D2, D4, etc.) are output at the falling edge of CLKOUTP and the odd data bits (D1, D3, D5, etc.) are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP must be used to capture all 14 data bits, as shown in Figure 114.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com LVDS Output Data and Clock Buffers The equivalent circuit of each LVDS output buffer is shown in Figure 115. After reset, the buffer presents an output impedance of 100Ω to match with the external 100Ω termination. The VDIFF voltage is nominally 350mV, resulting in an output swing of ±350mV with 100Ω external termination. The VDIFF voltage is programmable using the LVDS SWING register bits from ±125mV to ±570mV.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com Parallel CMOS Interface In CMOS mode, each data bit is output on a separate pin as the CMOS voltage level, for every clock cycle. The rising edge of the output clock CLKOUT can be used to latch data in the receiver. Figure 116 depicts the CMOS output interface. Switching noise (caused by CMOS output data transitions) can couple into the analog inputs and degrade SNR.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com Use External Clock Buffer (> 200MSPS) Input Clock Receiver (FPGA, ASIC, etc.) Flip-Flops CLKOUT CMOS Output Buffers D0 D1 D2 CLKIN D0_In D1_In D2_In 14-Bit ADC Data D12 D13 D12_In D13_In ADS414x Use short traces between ADC output and receiver pins (1 to 2 inches). Figure 117.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com Input Over-Voltage Indication (OVR Pin) The device has an OVR pin that provides information about analog input overload. At any clock cycle, if the sampled input voltage exceeds the positive or negative full-scale range, the OVR pin goes high. The OVR remains high as long as the overload condition persists.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com DEFINITION OF SPECIFICATIONS Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low-frequency value. Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. This delay is different across channels.
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ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A – FEBRUARY 2011 – REVISED MARCH 2011 www.ti.com Effective Number of Bits (ENOB) – ENOB is a measure of the converter performance as compared to the theoretical limit based on quantization noise. ENOB = SINAD - 1.76 6.02 (4) Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD). THD = 10Log10 PS PN (5) THD is typically given in units of dBc (dB to carrier).
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (3) 11-Apr-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS4122IRGZR VQFN RGZ 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS4122IRGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS4125IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS4122IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADS4122IRGZT VQFN RGZ 48 250 336.6 336.6 28.6 ADS4125IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADS4125IRGZT VQFN RGZ 48 250 336.6 336.6 28.6 ADS4142IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADS4142IRGZT VQFN RGZ 48 250 336.6 336.6 28.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.