Datasheet

ADS4122, ADS4125
ADS4142, ADS4145
www.ti.com SBAS520A –FEBRUARY 2011– REVISED MARCH 2011
ADS414x, ADS412x Pin Assignments (LVDS Mode)
PIN NAME PIN NUMBER # OF PINS FUNCTION DESCRIPTION
AVDD 8, 18, 20, 22, 24, 26 6 I 1.8V analog power supply
AGND 9, 12, 14, 17, 19, 25 6 I Analog ground
CLKP 10 1 I Differential clock input, positive
CLKM 11 1 I Differential clock input, negative
INP 15 1 I Differential analog input, positive
INM 16 1 I Differential analog input, negative
VCM 13 1 O Outputs the common-mode voltage (0.95V) that can be used externally to bias the analog input pins.
Serial interface RESET input.
When using the serial interface mode, the internal registers must initialize through hardware RESET by
applying a high pulse on this pin or by using the software reset option; refer to the Serial Interface
RESET 30 1 I section.
When RESET is tied high, the internal registers are reset to the default values. In this condition, SEN
can be used as an analog control pin.
RESET has an internal 180kΩ pull-down resistor.
This pin functions as a serial interface clock input when RESET is low. When RESET is high, SCLK
SCLK 29 1 I
has no function and should be tied to ground. This pin has an internal 180kΩ pull-down resistor.
This pin functions as a serial interface data input when RESET is low. When RESET is high, SDATA
SDATA 28 1 I
functions as a STANDBY control pin (see Table 7). This pin has an internal 180kΩ pull-down resistor.
This pin functions as a serial interface enable input when RESET is low. When RESET is high, SEN
SEN 27 1 I
has no function and should be tied to AVDD. This pin has an internal 180kΩ pull-up resistor to AVDD.
OE 7 1 I Output buffer enable input, active high; this pin has an internal 180kΩ pull-up resistor to DRVDD.
Data format select input. This pin sets the DATA FORMAT (twos complement or offset binary) and the
DFS 6 1 I
LVDS/CMOS output interface type. See Table 5 for detailed information.
RESERVED 23 1 I Digital control pin, reserved for future use
CLKOUTP 5 1 O Differential output clock, true
CLKOUTM 4 1 O Differential output clock, complement
Refer to Figure 1 and
D0_D1_P 1 O Differential output data D0 and D1 multiplexed, true
Figure 2
Refer to Figure 1 and
D0_D1_M 1 O Differential output data D0 and D1 multiplexed, complement
Figure 2
Refer to Figure 1 and
D2_D3_P 1 O Differential output data D2 and D3 multiplexed, true
Figure 2
Refer to Figure 1 and
D2_D3_M 1 O Differential output data D2 and D3 multiplexed, complement
Figure 2
Refer to Figure 1 and
D4_D5_P 1 O Differential output data D4 and D5 multiplexed, true
Figure 2
Refer to Figure 1 and
D4_D5_M 1 O Differential output data D4 and D5 multiplexed, complement
Figure 2
Refer to Figure 1 and
D6_D7_P 1 O Differential output data D6 and D7 multiplexed, true
Figure 2
Refer to Figure 1 and
D6_D7_M 1 O Differential output data D6 and D7 multiplexed, complement
Figure 2
Refer to Figure 1 and
D8_D9_P 1 O Differential output data D8 and D9 multiplexed, true
Figure 2
Refer to Figure 1 and
D8_D9_M 1 O Differential output data D8 and D9 multiplexed, complement
Figure 2
Refer to Figure 1 and
D10_D11_P 1 O Differential output data D10 and D11 multiplexed, true
Figure 2
Refer to Figure 1 and
D10_D11_M 1 O Differential output data D10 and D11 multiplexed, complement
Figure 2
Refer to Figure 1 and
D12_D13_P 1 O Differential output data D12 and D13 multiplexed, true
Figure 2
Refer to Figure 1 and
D12_D13_M 1 O Differential output data D12 and D13 multiplexed, complement
Figure 2
This pin functions as an out-of-range indicator after reset, when register bit
OVR_SDOUT 3 1 O
READOUT = 0, and functions as a serial register readout pin when READOUT = 1.
DRVDD 2, 35 2 I 1.8V digital and output buffer supply
DRGND 1, 36, PAD 2 I Digital and output buffer ground
Refer to Figure 1 and
NC — — Do not connect
Figure 2
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