Datasheet

ADS4122, ADS4125
ADS4142, ADS4145
SBAS520A FEBRUARY 2011 REVISED MARCH 2011
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TIMING REQUIREMENTS: LVDS and CMOS Modes
(1)
(continued)
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, sampling frequency = 125 MSPS, sine wave input clock,
C
LOAD
= 5pF
(2)
, and R
LOAD
= 100Ω
(3)
, unless otherwise noted. Minimum and maximum values are across the full temperature
range: T
MIN
= 40°C to T
MAX
= +85°C, AVDD = 1.8V, and DRVDD = 1.7V to 1.9V.
PARAMETER CONDITIONS MIN TYP MAX UNIT
DDR LVDS MODE (continued)
Duty cycle of differential clock, (CLKOUTP
LVDS bit clock duty
CLKOUTM) 48 %
cycle
Sampling frequency 125MSPS
Rise time measured from 100mV to +100mV
Data rise time,
t
RISE
, t
FALL
Fall time measured from +100mV to 100mV 0.14 ns
Data fall time
Sampling frequency 125MSPS
Output clock rise Rise time measured from 100mV to +100mV
t
CLKRISE
,
time, Fall time measured from +100mV to 100mV 0.14 ns
t
CLKFALL
Output clock fall time Sampling frequency 125MSPS
Output enable (OE) to
t
OE
Time to valid data after OE becomes active 50 100 ns
data delay
PARALLEL CMOS MODE
(8)
t
SETUP
Data setup time Data valid
(9)
to 50% of CLKOUT rising edge 3.1 3.7 ns
50% of of CLKOUT rising edge to data becoming
t
HOLD
Data hold time 3.2 4.0 ns
invalid
(9)
Input clock rising edge cross-over to 50% of output
Clock propagation
t
PDI
clock rising edge 4 5.5 7 ns
delay
Sampling frequency 125MSPS
Output clock duty Duty cycle of output clock, CLKOUT
47 %
cycle Sampling frequency 125MSPS
Rise time measured from 20% to 80% of DRVDD
Data rise time,
t
RISE
, t
FALL
Fall time measured from 80% to 20% of DRVDD 0.35 ns
Data fall time
Sampling frequency 125MSPS
Output clock rise Rise time measured from 20% to 80% of DRVDD
t
CLKRISE
,
time, Fall time measured from 80% to 20% of DRVDD 0.35 ns
t
CLKFALL
Output clock fall time Sampling frequency 125MSPS
Output enable (OE) to
t
OE
Time to valid data after OE becomes active 20 40 ns
data delay
(8) Low latency mode enabled.
(9) Data valid refers to a logic high of 1.25V and a logic low of 0.54V.
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