Datasheet

O
E
O
E
O
E
O
E
O
EE
O
E
O
E
O
E
O
E
O
N+1 N+2
InputClock
CLKOUTM
CLKOUTP
OutputData
(2)
(DXP,DXM)
DDRLVDS
N 1- N N+1
CLKOUT
OutputData
ParallelCMOS
InputSignal
SampleN
N+1
N+2
N+3 N+4
N+10
N+11
N+12
t
A
t
SU
t
SU
t
H
t
H
t
PDI
t
PDI
CLKP
CLKM
N 10- N 9- N 8- N 7-
N 10- N 9- N 8-
N 7-
N 6-
10ClockCycles
(1)
N
10ClockCycles
(1)
ADS4122, ADS4125
ADS4142, ADS4145
www.ti.com SBAS520A –FEBRUARY 2011– REVISED MARCH 2011
Table 2. LVDS Timing Across Sampling Frequencies
SAMPLING SETUP TIME (ns) HOLD TIME (ns)
FREQUENCY
(MSPS) MIN TYP MAX MIN TYP MAX
65 5.5 6.5 0.35 0.60
80 4.50 5.20 0.35 0.60
Table 3. CMOS Timing Across Sampling Frequencies (Low Latency Enabled)
TIMING SPECIFIED WITH RESPECT TO OUTPUT CLOCK
SAMPLING
t
SETUP
(ns) t
HOLD
(ns) t
PDI
(ns)
FREQUENCY
(MSPS) MIN TYP MAX MIN TYP MAX MIN TYP MAX
65 6.5 7.5 6.5 7.5 4.0 5.5 7.0
80 5.4 6.0 5.4 6.0 4.0 5.5 7.0
Table 4. CMOS Timing Across Sampling Frequencies (Low Latency Disabled)
TIMING SPECIFIED WITH RESPECT TO OUTPUT CLOCK
SAMPLING
t
SETUP
(ns) t
HOLD
(ns) t
PDI
(ns)
FREQUENCY
(MSPS) MIN TYP MAX MIN TYP MAX MIN TYP MAX
65 6 7 7 8 4.0 5.5 7.0
80 4.8 5.5 5.7 6.5 4.0 5.5 7.0
125 2.5 3.2 3.5 4.3 4.0 5.5 7.0
(1) ADC latency in low-latency mode. At higher sampling frequencies, t
DPI
is greater than one clock cycle which then makes the overall
latency = ADC latency + 1.
(2) E = Even bits (D0, D2, D4, etc). O = Odd bits (D1, D3, D5, etc).
Figure 8. Latency Diagram
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