Datasheet

ADS4122, ADS4125

ADS4142, ADS4145

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SBAS520A –FEBRUARY 2011– REVISED MARCH 2011

7 6 5 4 3 2 1 0

GAIN DISABLE GAIN TEST PATTERNS

Bits[7:4] GAIN: Gain programmability

These bits set the gain programmability in 0.5dB steps.

0000 = 0dB gain (default after reset) 0111 = 3.5dB gain

0001 = 0.5dB gain 1000 = 4.0dB gain

0010 = 1.0dB gain 1001 = 4.5dB gain

0011 = 1.5dB gain 1010 = 5.0dB gain

0100 = 2.0dB gain 1011 = 5.5dB gain

0101 = 2.5dB gain 1100 = 6dB gain

0110 = 3.0dB gain

Bit 3 DISABLE GAIN: Gain setting

This bit sets the gain.

0 = Gain enabled; gain is set by the GAIN bits only if low-latency mode is disabled

1 = Gain disabled

Bits[2:0] TEST PATTERNS: Data capture

These bits verify data capture.

000 = Normal operation

001 = Outputs all 0s

010 = Outputs all 1s

011 = Outputs toggle pattern

In the ADS4122/25, output data D[11:0] is an alternating sequence of 010101010101 and

101010101010.

In the ADS4142/45, output data D[13:0] is an alternating sequence of 01010101010101 and

10101010101010.

100 = Outputs digital ramp

In ADS4122/25, output data increments by one LSB (12-bit) every fourth clock cycle from code 0

to code 4095

In ADS4142/45, output data increments by one LSB (14-bit) every clock cycle from code 0 to

code 16383

101 = Output custom pattern (use registers 3Fh and 40h for setting the custom pattern)

110 = Unused

111 = Unused

Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145