Datasheet

0 0.5 1 1.5 2 2.5 3 3.5 4
73
75
77
79
81
83
85
87
89
91
93
95
62
63
64
65
66
67
68
69
70
71
72
73
Differential Clock Amplitude (V
PP
)
SFDR (dBc)
SNR (dBFS)
SFDR
SNR
Input Frequency = 150MHz
63
64
65
66
67
68
69
70
71
72
73
30 35 40 45 50 55 60 65 70
Input Clock Duty Cycle (%)
SNR (dBFS)
Default
Low−Speed Mode Enabled
Input Frequency = 10MHz
ADS4122, ADS4125
ADS4142, ADS4145
www.ti.com SBAS520A –FEBRUARY 2011– REVISED MARCH 2011
TYPICAL CHARACTERISTICS: ADS4125 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5V
PP
differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted.
PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE SNR ACROSS INPUT CLOCK DUTY CYCLE
Figure 49. Figure 50.
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Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145