Datasheet
0 0.5 1 1.5 2 2.5 3 3.5
73
75
77
79
81
83
85
87
89
91
58
60
62
64
66
68
70
72
74
76
Differential Clock Amplitude (V
PP
)
SFDR (dBc)
SNR (dBFS)
SFDR
SNR
Input Frequency = 150MHz
40 45 50 55 60
78
82
86
90
94
72.5
73
73.5
74
74.5
Input Clock Duty Cycle (%)
THD (dBc)
SNR (dBFS)
THD
SNR
Input Frequency = 10MHz
−1.5
−1
−0.5
0
0.5
1
1.5
0 2048 4096 6144 8192 10240 12288 14336 16384
Output Code (LSB)
INL (LSB)
0
OutputCode(LSB)
8168 8176
CodeOccurrence(%)
81718170 8174
50
10
15
20
25
30
5
81738172 8175
45
40
35
8169
ADS4122, ADS4125
ADS4142, ADS4145
SBAS520A –FEBRUARY 2011– REVISED MARCH 2011
www.ti.com
TYPICAL CHARACTERISTICS: ADS4142 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5V
PP
differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted.
PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE
Figure 67. Figure 68.
OUTPUT NOISE HISTOGRAM
INTEGRAL NONLINEARITY (with Inputs Shorted to VCM)
Figure 69. Figure 70.
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Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145