Datasheet

D10_D11_M
D10_D11_P
D8_D9_M
D8_D9_P
D6_D7_M
D6_D7_P
D4_D5_M
D4_D5_P
D2_D3_M
D2_D3_P
D0_D1_M
D0_D1_P
CLKOUTM
DataBitsD10,D11
DataBitsD8,D9
DataBitsD6,D7
DataBitsD4,D5
DataBitsD2,D3
DataBitsD0,D1
OutputClock
CLKOUTP
Pins
ADS412x
LVDSBuffers
12-Bit
ADCData
D10_D11_M
D10_D11_P
D8_D9_M
D8_D9_P
D6_D7_M
D6_D7_P
D4_D5_M
D4_D5_P
D2_D3_M
D2_D3_P
D0_D1_M
D0_D1_P
CLKOUTM
DataBitsD10,D11
DataBitsD8,D9
DataBitsD6,D7
DataBitsD4,D5
DataBitsD2,D3
DataBitsD0,D1
OutputClock
CLKOUTP
Pins
ADS414x
LVDSBuffers
14-Bit
ADCData
D12_D13_M
D12_D13_P
DataBitsD12,D13
ADS4122, ADS4125
ADS4142, ADS4145
SBAS520A –FEBRUARY 2011– REVISED MARCH 2011 www.ti.com
DIGITAL OUTPUT INFORMATION
The ADS412x/4x provide either 14-bit data or 12-bit data, respectively, and an output clock synchronized with the
data.
Output Interface
Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. They can be
selected using the LVDS CMOS serial interface register bit or using the DFS pin.
DDR LVDS Outputs
In this mode, the data bits and clock are output using low voltage differential signal (LVDS) levels. Two data bits
are multiplexed and output on each LVDS differential pair, as shown in Figure 112 and Figure 113.
Figure 112. ADS412x LVDS Data Outputs
Figure 113. ADS414x LVDS Data Outputs
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Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145