Datasheet

V
DIFF
V
DIFF
1.1V
High
Low
Low
High
OUTP
OUTM
R
OUT
External
100 LoadW
ADS4122, ADS4125
ADS4142, ADS4145
SBAS520A –FEBRUARY 2011– REVISED MARCH 2011 www.ti.com
LVDS Output Data and Clock Buffers
The equivalent circuit of each LVDS output buffer is shown in Figure 115. After reset, the buffer presents an
output impedance of 100Ω to match with the external 100Ω termination.
The V
DIFF
voltage is nominally 350mV, resulting in an output swing of ±350mV with 100Ω external termination.
The V
DIFF
voltage is programmable using the LVDS SWING register bits from ±125mV to ±570mV.
Additionally, a mode exists to double the strength of the LVDS buffer to support 50Ω differential termination. This
mode can be used when the output LVDS signal is routed to two separate receiver chips, each using a 100Ω
termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS CLKOUT STRENGTH
register bits for data and output clock buffers, respectively.
The buffer output impedance behaves in the same way as a source-side series termination. By absorbing
reflections from the receiver end, it helps to improve signal integrity.
NOTE: Use the default buffer strength to match 100Ω external termination (R
OUT
= 100Ω). To match with a 50Ω external termination, set the
LVDS STRENGTH bit (R
OUT
= 50Ω).
Figure 115. LVDS Buffer Equivalent Circuit
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